3D Memory Connection Region Layout for Arcing and Crack Suppression
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Solution Overview
Problem
Current semiconductor memory devices face challenges in preventing arcing during high aspect ratio memory hole formation, which can lead to wafer destruction, and in managing electrical resistances and crack propagation during the dicing process, affecting integration and reliability.
Innovation Solution
The semiconductor memory device incorporates a connection region with alternating first and second regions and specific insulating and conductive layer configurations, including openings and conductive layers, to manage charge release and reduce electrical resistances, and employs a manufacturing method that forms openings in the insulating layer to control crack propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high aspect ratio memory holes are formed to increase integration density, then integration density is improved, but arcing occurs during formation which can lead to wafer destruction
Solution Approach 1:
The semiconductor substrate is divided into multiple regions (first region with memory cells, second region as buffer zone, third region as transition zone). This segmentation allows the high aspect ratio memory holes to be formed only in the first region while the other regions provide protective functions to prevent arcing and crack propagation.
Solution Approach 2:
The second region acts as an intermediary buffer zone between the memory cell region and the substrate edge. It includes conductive layers and openings that mediate charge release, preventing direct arcing in the memory holes while maintaining the high aspect ratio structure needed for integration density.
2Reliability
If conductive layers are added to manage charge release, then reliability is improved, but device complexity increases
Solution Approach 1:
The conductive layers formed in the second and third regions serve multiple functions: they manage charge release during memory hole formation, act as electrical connections, and provide structural support. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while improving reliability.
Solution Approach 2:
The patent combines the charge release function with the existing conductive layer structure. Instead of adding separate charge release mechanisms, the conductive layers are integrated into the memory hole formation process, merging multiple functions into a unified structure that manages complexity.
3Reliability
If openings are formed in insulating layers to control crack propagation, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The openings in the insulating layers are formed in advance during the insulating layer formation process, before the dicing process occurs. This preliminary action ensures that the openings are already in place to guide and control crack propagation paths, reducing the precision requirements during subsequent dicing operations.
Data Source
AI summary
A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction. In the second portions, the fifth and the sixth semiconductor layers are electrically connected.