3D Memory Contact Region Asymmetry for Voltage Drop Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reliability due to variations in voltage drop across word line fingers, leading to malfunctions and reduced processing capacity, particularly in three-dimensional stacked memory configurations.
Innovation Solution
The semiconductor memory device incorporates a specific configuration where the contact region portions for word line combs are strategically placed, with the uppermost contact region portion located closer to the center and the lowermost in the end region, reducing voltage variation and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact region portions are placed in conventional positions in three-dimensional stacked memory, then device complexity is reduced, but voltage drop variations increase leading to reliability degradation
Solution Approach 1:
The patent applies local quality by differentiating the positions of contact region portions for different word line combs. Specifically, contact region portions for odd-numbered word line combs are placed at first positions while even-numbered word line combs have contact region portions at second positions. This asymmetric arrangement compensates for voltage drop variations that occur in different regions of the stacked memory structure, thereby improving device reliability without requiring a completely new configuration paradigm.
2Reliability
If contact region portions are strategically repositioned to reduce voltage variation, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the contact region positioning into distinct groups based on word line comb numbering. Odd-numbered word line combs share a common contact region position pattern while even-numbered combs follow another pattern. This segmentation approach simplifies the manufacturing process by reducing the number of unique positioning requirements, thereby improving reliability without proportionally increasing manufacturing precision demands.
3Productivity
If conventional contact region arrangement is used, then ease of manufacture is maintained, but processing capacity and reliability deteriorate due to voltage drop variations
Solution Approach 1:
The patent introduces asymmetry in the contact region arrangement by placing contact regions at different positions for odd and even word line combs. This asymmetric configuration optimizes voltage distribution across the stacked memory structure, enabling higher processing capacity and improved reliability. The systematic nature of the asymmetric arrangement (based on comb numbering) maintains reasonable manufacturing simplicity while achieving superior performance.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.