Memory Contact Structure Layout for Lower Bit Line Resistance
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Solution Overview
Problem
Current methods for forming memory devices face challenges in optimizing the contact structure to enhance conductivity and reduce resistance, which affects the overall performance of the memory device.
Innovation Solution
A method involving the formation of a contact structure with a middle portion at a height substantially level with the gate structure, increasing the contact area and using a multi-layer conductive material deposition process to fill openings, thereby improving conductivity and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional contact structure is used in memory device formation, then the manufacturing process is simpler, but the contact area is smaller and resistance is higher
Solution Approach 1:
The contact structure is divided into three distinct portions: a bottom portion formed above the peripheral conductive line, a middle portion formed at the same height as the gate structure, and a top portion connecting to the bit line. This segmentation increases the total contact area and reduces resistance by creating multiple conductive pathways through different structural levels.
Solution Approach 2:
The contact structure extends across multiple vertical dimensions and horizontal levels. The middle portion is positioned at the same height as the gate structure, creating a multi-level contact architecture that increases contact area without proportionally increasing planar footprint, thereby reducing resistance while managing structural complexity.
2Reliability
If the contact area is increased to reduce resistance, then the conductivity improves, but the manufacturing process becomes more complex
Solution Approach 1:
The formation of the first opening, second opening, gate material, and gate structure are combined into a single integrated process sequence. The conductive material is deposited to form both the middle portion of the contact structure and the gate structure simultaneously, reducing the number of separate manufacturing steps while achieving increased contact area.
Solution Approach 2:
The gate structure serves dual functions: as the control electrode for the transistor and as a reference level for positioning the middle portion of the contact structure. This multi-functionality allows the contact structure to achieve increased contact area while utilizing existing structural elements, thereby reducing overall manufacturing complexity.
Data Source
AI summary
A method includes forming a first conductive line and a second conductive respectively above a memory region and a peripheral region of a substrate. A capacitor is formed above the first conductive line. A bottom portion of a contact structure is formed above the second conductive line. A first dielectric layer is formed covering the capacitor and the bottom portion. First and second openings are formed in the first dielectric layer. The first opening is above the capacitor, and the second opening exposes the bottom portion. A middle portion of the contact structure and a gate material are respectively formed in the second opening and the first opening. A third opening is formed in the gate material to form a gate structure. A gate dielectric layer and a channel are formed in the third opening. A bit line is connected to the channel and the contact structure.