Memory Cell Contact Structure With Etch-Stop Insulating Layers
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Solution Overview
Problem
Current semiconductor storage devices face challenges in reducing size and maintaining high signal transmission speed due to limitations in the design of penetrating contact structures and inter-block structures, which affect electrical resistance and device compactness.
Innovation Solution
The semiconductor storage device incorporates a penetrating contact structure with a rectangular cylindrical shape formed by stopper insulating layers, allowing for a shorter length and narrower width, and an inter-block structure with adjusted positions to increase the width of adjacent wiring regions, thereby reducing device size and maintaining high signal transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the penetrating contact structure is made shorter and narrower to reduce device size, then the device size is reduced, but the electrical resistance increases
Solution Approach 1:
The penetrating contact structure uses a composite configuration combining multiple materials: a first conductive layer (e.g., tungsten) filled in a contact hole through the insulating layer, and a second conductive layer (e.g., copper) formed above it. This composite structure allows the contact to maintain low electrical resistance while being compact, as each material contributes its advantageous properties (tungsten provides low resistance through the insulating layer, copper provides low resistance in the upper region).
Solution Approach 2:
The penetrating contact structure implements a nested configuration where the first conductive layer is embedded within the insulating layer (contact hole), and the second conductive layer is formed above it, creating a nested arrangement of conductive elements. This nesting allows the contact structure to achieve effective electrical connection through a compact vertical arrangement, reducing the overall footprint while maintaining low resistance.
2Speed
If the inter-block structure positions are adjusted to increase wiring region width, then the signal transmission speed is improved, but the device size increases
Solution Approach 1:
The inter-block structure utilizes vertical stacking to achieve its function rather than requiring additional horizontal space. By forming insulating layers and conductive layers in alternating stacked arrangements in the vertical direction, the design maintains compact planar dimensions while providing sufficient wiring region width for high-speed signal transmission through the three-dimensional layout.
Solution Approach 2:
The inter-block structure serves multiple functions simultaneously: it provides electrical isolation between adjacent blocks through insulating layers, establishes electrical connections through conductive layers, and defines wiring regions for signal transmission. This multi-functionality allows the structure to achieve high signal transmission speed without proportionally increasing device size, as a single structural element performs multiple critical roles.
3Ease of manufacture
If chemical etching solutions are used for manufacturing, then the manufacturing process is simplified, but unwanted etching of adjacent regions occurs
Solution Approach 1:
The insulating layer serves as an intermediary barrier during the chemical etching process. It is selectively positioned and patterned to protect adjacent regions from unwanted etching while allowing the etching solution to access and remove material in the desired contact hole regions. This intermediary structure enables the use of simplified chemical etching processes without the harmful side effects of uncontrolled etching propagation.
Solution Approach 2:
The insulating layer is applied with spatially varying properties and positions: it is present in some regions to protect against etching, and absent in other regions (contact holes) to allow etching. This local differentiation of the insulating layer's presence and characteristics enables selective etching, achieving simple manufacturing processes while preventing unwanted etching in protected regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the size of the semiconductor storage device while ensuring high electrical resistance and signal transmission speed by blocking chemical etching solutions and optimizing the layout of insulating layers and conductive layers.
Implementation Method 1
In a replace process, a part of the insulating layers 101 is removed by chemical etching or the like
Data Source
AI summary
A semiconductor storage device includes a substrate and a memory cell array. The memory cell array is above the substrate in a first direction. The memory cell array includes first to third regions arranged in a second direction. The memory cell array comprises a first stack in the first and third regions, first and second semiconductor layers extending through the first stack in the first and third regions, respectively, a second stack in the second region, a first contact extending through the second stack, a fourth insulating layer extending in the first and second directions in the second region, and a fifth insulating layer extending in the first direction and a third direction in the second region. A distance from a bottom end of the fourth insulating layer to the substrate is different from a distance from a bottom end of the fifth insulating layer to the substrate.