3D Memory Gate Stack Contact Isolation for Dense Word-Line Arrays
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Solution Overview
Problem
The increasing complexity of manufacturing processes in three-dimensional semiconductor memory devices due to the stacking of numerous word lines complicates the integration density improvement.
Innovation Solution
A semiconductor memory device structure featuring a substrate with a peripheral circuit, a gate stack structure, a channel structure, a memory layer surrounding the channel structure, and insulating structures around contact plugs, along with a manufacturing method that includes forming a preliminary structure, a stack structure, and channel and contact plugs, simplifying the process by etching in stages to form channel and contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on top of each other is increased to improve integration density, then the integration density is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into multiple etching stages: first forming channel holes through the gate stack structure, then forming contact holes through the channel structure. This segmentation allows each etching process to be optimized independently, reducing overall manufacturing complexity while enabling higher word line stacking
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertical stacking of word lines. By utilizing the vertical dimension, integration density is dramatically improved without proportionally increasing manufacturing process complexity, as the same etching and deposition processes are applied in a stacked configuration
2Area of stationary object
If more word lines are stacked to improve integration density, then the integration density is improved, but the manufacturing process becomes more complicated
Solution Approach 1:
The gate stack structure is formed preliminarily before etching the channel and contact holes. This preliminary formation of the gate stack with multiple stacked word lines allows subsequent etching processes to proceed through pre-defined structures, simplifying the manufacturing process despite the increased number of stacked layers
Solution Approach 2:
The channel structure is formed within the channel holes of the gate stack structure, and contact plugs are formed within the contact holes that pass through the channel structure. This nested arrangement allows multiple functional elements to be integrated vertically without proportionally increasing manufacturing complexity
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.