3D Memory Contact Layout to Reduce Dielectric Breakdown
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in efficiently transferring voltage across memory blocks due to long distances between contact and through contact regions, leading to potential dielectric breakdown and complex wiring patterns.
Innovation Solution
The semiconductor memory device employs a staggered pattern of contact and through contact regions, reducing voltage differences across insulating layers and simplifying wiring by arranging these regions in a staggered configuration, thereby minimizing dielectric breakdown risk and circuit area while optimizing wiring efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact and through contact regions are arranged in a conventional non-staggered pattern, then wiring connections can be established, but voltage differences across insulating layers increase leading to dielectric breakdown risk
Solution Approach 1:
The patent applies asymmetry by arranging contact regions and through contact regions in a staggered pattern rather than aligning them directly. This asymmetric arrangement reduces voltage differences across insulating layers between adjacent memory blocks, preventing dielectric breakdown while simplifying the overall wiring pattern.
Solution Approach 2:
The patent utilizes spatial arrangement in multiple dimensions by staggering contact and through contact regions across different locations and depths. This dimensional optimization allows voltage transfer paths to be distributed more effectively, reducing peak voltage differences without increasing wiring complexity.
2Length of stationary object
If contact and through contact regions are positioned close together, then wiring distance is reduced, but voltage differences across insulating layers increase causing dielectric breakdown
Solution Approach 1:
By positioning contact and through contact regions in a staggered asymmetric pattern rather than directly overlapping or aligned positions, the patent achieves optimal spacing that reduces voltage differences across insulating layers while maintaining reasonable wiring distances.
3Reliability
If a staggered pattern of contact and through contact regions is implemented, then voltage differences are reduced and dielectric breakdown is minimized, but wiring layout complexity increases
Solution Approach 1:
The staggered asymmetric arrangement of contact and through contact regions actually simplifies the wiring pattern by eliminating the need for complex routing around aligned structures, while simultaneously reducing voltage differences and preventing dielectric breakdown.
Data Source
AI summary
A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.