Vertical Memory Contact Layout With Floating Preliminary Contacts
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Solution Overview
Problem
Existing vertical memory devices face challenges in efficiently changing the number or positions of effective contact structures, which can lead to increased manufacturing time and costs, as well as defects in the contact structures.
Innovation Solution
The proposed solution involves a memory device design where effective contact structures and preliminary contact structures are integrated, allowing for easy modification of the number or positions of effective contact structures by modifying only the semiconductor masks corresponding to the lower and upper interconnection structures, without altering the masks for the contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number or positions of effective contact structures are changed by modifying contact structure masks, then the adaptability of the memory device is improved, but the manufacturing time and costs increase
Solution Approach 1:
The patent applies preliminary action by pre-forming both effective contact structures and preliminary contact structures (dummy contacts) through the interlayer insulating layer before interconnection formation. This allows the contact structure mask to remain unchanged while adaptability is achieved by selectively connecting preliminary contact structures to circuit components through modifiable interconnection patterns, thereby reducing manufacturing time and costs associated with repeated mask modifications.
2Adaptability or versatility
If the number or positions of effective contact structures are changed by modifying contact structure masks, then the adaptability of the memory device is improved, but the manufacturing costs increase
Solution Approach 1:
The patent applies preliminary action by pre-forming both effective contact structures and preliminary contact structures (dummy contacts) through the interlayer insulating layer before interconnection formation. This allows the contact structure mask to remain unchanged while adaptability is achieved by selectively connecting preliminary contact structures to circuit components through modifiable interconnection patterns, thereby reducing manufacturing costs associated with repeated mask modifications.
3Device complexity
If only effective contact structures are formed without preliminary contact structures, then the device complexity is reduced, but the reliability of contact structures decreases due to increased defects
Solution Approach 1:
The patent applies the intermediary principle by introducing preliminary contact structures as mediator elements that perform dual functions: they serve as dummy contacts to improve etching uniformity and reduce defects in effective contact structures, while also potentially serving as backup contact paths. This intermediary structure resolves the contradiction by enhancing reliability without significantly increasing overall device complexity, as the preliminary contact structures use the same formation process as effective contact structures.
4Reliability
If preliminary contact structures are added to improve etching uniformity, then the reliability of contact structures is improved, but the device complexity increases
Solution Approach 1:
The patent applies the merging principle by combining the formation of effective contact structures and preliminary contact structures into a single simultaneous process step using a common mask pattern. Both types of contact structures are formed through the same etching process through the interlayer insulating layer, eliminating the need for separate process steps. This merging approach improves reliability through better etching uniformity while minimizing the increase in device complexity, as the additional structures are created without adding process complexity.
Data Source
AI summary
An example memory device includes a lower interconnection structure on a substrate, a cell stack structure on the lower interconnection structure, an interlayer insulating layer covering the cell stack structure, an upper interconnection structure on the interlayer insulating layer, one or more effective contact structures respectively passing through the interlayer insulating layer, and one or more preliminary contact structures respectively passing through the interlayer insulating layer. The lower interconnection structure includes circuit components and lower conductive patterns. The cell stack structure includes gate electrodes stacked and spaced apart from each other in a vertical direction. The vertical direction is perpendicular to an upper surface of the substrate. The upper interconnection structure includes upper conductive patterns and one or more external pads. The one or more preliminary contact structures are electrically floating.


