Nonvolatile Memory Contact Layout for High Density and Low Leakage
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Solution Overview
Problem
As semiconductor devices become lighter, thinner, and more integrated, leakage currents occur, necessitating improved control to enhance performance and reliability, and there is a desire for increased data storage capacity, particularly through three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor device design featuring a substrate with specific conductive line configurations, including lower contacts with smaller dimensions in one direction and larger dimensions in another direction, and conductive lines extending parallel to the substrate surface, which are connected to transistors and bit-lines in a non-volatile memory device, optimizing chip size and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component sizes are decreased to increase integration, then integration density is improved, but leakage current increases
Solution Approach 1:
The patent applies different contact width dimensions in different directions: the lower contact has a first width in the first direction and a second width in the second direction, where the second width is greater than the first width. This asymmetric local quality optimization allows the contact to maintain sufficient conductivity while minimizing footprint, enabling higher integration without proportionally increasing leakage current.
Solution Approach 2:
The patent transitions from isotropic contact design to anisotropic design by introducing different width measurements in different directions (first direction vs. second direction). This dimensional differentiation allows the contact structure to optimize both area efficiency and electrical performance simultaneously, resolving the contradiction between integration density and leakage current control.
2Area of stationary object
If chip size is reduced to meet lighter and thinner requirements, then portability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The lower contact is designed with asymmetric dimensions where the width in the second direction exceeds the width in the first direction. This asymmetric geometry allows the contact to achieve sufficient electrical connection area while maintaining a compact overall footprint, enabling chip size reduction without compromising manufacturing feasibility.
Solution Approach 2:
The patent changes the geometric parameters of the contact structure by specifying different width values in different directions. This parameter differentiation allows optimization of the contact's electrical and mechanical properties independently, achieving reliable connections in smaller chip formats with controlled manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes: a substrate includes an active area; a gate structure intersecting the active area; a source/drain area disposed on the active area; a lower contact disposed on the source/drain area or the gate structure; an upper contact disposed on the lower contact; and a plurality of conductive lines disposed on the upper contact, wherein the plurality of conductive lines extend in a first direction parallel to an upper surface of the substrate, wherein the plurality of conductive lines includes a first conductive line disposed on the upper contact, wherein a size in the first direction of the lower contact is smaller than a size in the first direction of the upper contact, wherein a size in a second direction of the lower contact is greater than a size in the second direction of the upper contact, wherein the second direction intersects the first direction.