3D Memory Contact Region Reduction via Mark Region Alignment
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Solution Overview
Problem
In three-dimensional memory devices, the increase in the number of stacked conductive layers leads to a larger contact region, which in turn increases the chip area, making it necessary to reduce the contact region area while maintaining precise alignment and positioning of conductive layers to avoid short circuits and misalignment issues.
Innovation Solution
The implementation of a storage device with a stacked body having conductive layers forming different step structures in distinct regions, along with a mark region for precise alignment and dimension measurement during the lithography process, allows for the reduction of the contact region area by accurately controlling the positioning of electrodes perpendicular to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked conductive layers is increased to achieve large integration, then the storage capacity is improved, but the area of the contact region increases
Solution Approach 1:
The contact region is divided into multiple contact holes distributed across different levels, with each contact hole connecting to specific conductive layers. This segmentation allows the contact function to be distributed rather than concentrated in one large region, reducing the overall contact region area while maintaining connectivity to all necessary conductive layers.
Solution Approach 2:
The patent transitions from a two-dimensional contact layout to a three-dimensional structure by forming contact holes at different depths and positions that connect to stacked conductive layers vertically. This dimensional change allows multiple contact points to be arranged in a compact footprint by utilizing the vertical stacking dimension, thereby reducing the planar contact region area.
2Area of stationary object
If the contact region area is reduced to decrease chip area, then the chip area is improved, but the alignment precision between electrodes and conductive layers deteriorates
Solution Approach 1:
A mark region is formed in advance before the contact holes are etched. This mark region serves as a reference for alignment measurement and control in subsequent lithography processes. By establishing this reference structure beforehand, the patent enables precise positioning of contact holes relative to the stacked conductive layers, maintaining high alignment precision even in the reduced contact region.
Solution Approach 2:
The mark region is used to measure misalignment between the contact holes and the stacked conductive layers. This measurement provides feedback that can be used to adjust and control the alignment in subsequent processing steps, ensuring that the contact holes are precisely positioned despite the reduced contact region area.
3Area of stationary object
If the contact region area is reduced, then the chip area is improved, but the risk of short circuits and misalignment issues increases
Solution Approach 1:
The mark region acts as an intermediary reference structure between the contact holes and the stacked conductive layers. It provides a measurable reference that enables precise alignment control, thereby reducing the risk of misalignment-induced short circuits. The mark region mediates the positioning process, ensuring accurate placement of contact holes in the reduced contact region.
Solution Approach 2:
By forming the mark region and establishing alignment references before creating the contact holes, the patent proactively prevents misalignment and short circuit issues. This preliminary action allows for measurement and correction of potential alignment problems before the actual contact structures are formed, enhancing reliability in the compact design.
Data Source
AI summary
A storage device according to embodiments includes a substrate, a stacked body, a first region, a second region, and first to nth electrodes. The stacked body is provided on the substrate and having first to nth (n is an integer of 3 or more) conductive layers stacked in a direction perpendicular to a surface of the substrate. The first region includes a part of the stacked body, and has a first step structure including the first to the nth conductive layers. The second region includes a part of the stacked body, and has a second step structure different from the first step structure including at least a part of the first to nth conductive layers. The first to nth electrodes are provided in the first region and connected to the first to nth conductive layers and extend in a direction perpendicular to the surface of the substrate.