3D Memory Contact Hole Layout for Overlay Shift Correction
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Solution Overview
Problem
The existing manufacturing processes for semiconductor memory face challenges in accurately measuring and correcting overlay shifts during the formation of contact holes, which can lead to short circuits and reduced yield due to the variation in the position of boundaries between terraced portions in the staircase configuration of word lines.
Innovation Solution
The method involves forming contact holes with a larger diameter in dummy blocks not used for data storage, allowing for non-destructive evaluation of overlay shifts using a scanning electron microscope, and feeding back correction values to improve lithography processes, thereby enhancing yield and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If contact holes are formed in dummy blocks with larger diameter for overlay measurement, then measurement precision is improved, but device complexity increases due to additional measurement and correction processes
Solution Approach 1:
The patent forms contact holes with larger diameter in dummy blocks before final lithography processes, enabling preliminary overlay measurement and correction. This preliminary action allows detection of boundary position variations between terraced portions of word lines, and correction values are calculated and applied to subsequent lithography steps to prevent short circuits in active memory regions.
Solution Approach 2:
The patent introduces dummy blocks as intermediary structures that contain contact holes with larger diameter specifically for overlay measurement purposes. These dummy blocks serve as a mediator between the lithography process and overlay measurement system, allowing non-destructive evaluation of overlay shifts without affecting the active memory cell regions.
2Reliability
If overlay shifts are not corrected, then manufacturing process is simpler, but reliability decreases due to short circuits from misaligned contact holes
Solution Approach 1:
The patent implements a feedback mechanism where overlay shifts are measured using contact holes in dummy blocks, correction values are calculated based on the measured boundary position variations, and these correction values are applied to subsequent lithography processes. This closed-loop feedback system continuously monitors and corrects overlay alignment, preventing short circuits between contact holes and word lines, thereby improving yield without significantly complicating the manufacturing process.
3Manufacturing precision
If contact holes are formed with precise alignment, then manufacturing precision is improved, but measurement capability deteriorates due to inability to detect overlay shifts
Solution Approach 1:
The patent segments the wafer surface into active memory regions and dummy measurement regions. The dummy blocks contain contact holes with larger diameter specifically designed for overlay measurement, while active regions contain normally-sized contact holes for data storage. This segmentation allows simultaneous pursuit of precise alignment in active regions and measurement capability in dummy regions, as the two functions are spatially separated.
Data Source
AI summary
A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.