Semiconductor Memory Contact Pad Layout for Wiring Density
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Solution Overview
Problem
The increasing complexity of semiconductor memory devices requires improved electrical characteristics, but the spatial limitations due to bit line contact pads hinder the increase in the number and pitch of wiring lines, which affects power and signal transfer characteristics.
Innovation Solution
The semiconductor memory device design includes bit line contact pads and first contact pads arranged in a specific layout, allowing for an increased number and pitch of wiring lines without expanding the device size, by strategically positioning at least two first contact pads corresponding to two bit line contact pads in a line, thereby enhancing power and signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number and pitch of wiring lines are increased to improve electrical characteristics, then the device complexity and wiring capability are improved, but the spatial limitations due to bit line contact pads prevent further increase without expanding device size
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar arrangement of contact pads to a three-dimensional stacked configuration. Bit line contact pads are positioned at different vertical levels (first plane and second plane) rather than all on the same plane, enabling wiring lines to be routed in multiple layers and directions without increasing the footprint area. This vertical stacking allows increased wiring density and pitch while maintaining the same device footprint.
2Productivity
If the device size is kept constant to maintain manufacturing efficiency, then the manufacturing cost and process complexity are controlled, but the ability to increase wiring lines for improved electrical characteristics is limited
Solution Approach 1:
The patent segments the contact pad structure into multiple independent contact pads positioned at different planes and locations. Instead of using a single large contact area, the design divides the electrical connection function across multiple smaller contact pads (first contact pads on first plane, second contact pads on second plane). This segmentation allows independent routing of multiple wiring lines through different spatial paths, increasing the number of wiring lines and improving electrical characteristics while maintaining the same overall device footprint for manufacturing efficiency.
Data Source
AI summary
A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.