3D Memory Contact Plug Structure for Gate Insulation Reliability
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and reliability, particularly in the design of gate electrodes and channel structures.
Innovation Solution
A semiconductor device with a unique structure featuring stacked gate electrodes, channel structures penetrating through these electrodes, and contact plugs with varying widths, surrounded by spacer layers made of a different material than the peripheral insulating layer, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs have uniform width throughout their structure, then manufacturing is simpler, but electrical connectivity and structural integrity are compromised
Solution Approach 1:
The contact plug is divided into three distinct portions (first, second, and third portions) with different widths. The first portion has a first width, the second portion has a second width smaller than the first width, and the third portion has a third width greater than the second width. This segmentation allows each portion to serve different functional purposes, improving electrical connectivity and structural integrity while managing complexity through deliberate structural division.
Solution Approach 2:
Different portions of the contact plug are given different local properties through varying widths. The narrower second portion provides better electrical connectivity and stress distribution, while the wider first and third portions provide structural support and stability. This local quality variation optimizes both connectivity and structural integrity without requiring complete structural redesign.
2Reliability
If spacer layers use the same material as peripheral region insulating layer, then manufacturing process is simpler, but electrical insulation performance is reduced
Solution Approach 1:
The spacer layers are formed using a first insulating material that differs from the peripheral region insulating layer's second insulating material. This local quality differentiation ensures that the spacer layers provide superior electrical insulation performance in critical areas where contact plugs interface with gate electrodes, while the peripheral region maintains its own insulation characteristics. The different materials are deposited using sequential CVD processes, managing manufacturing complexity through standardized deposition techniques.
Solution Approach 2:
The device employs a composite material structure where spacer layers use a first insulating material (e.g., silicon nitride) and the peripheral region insulating layer uses a second insulating material (e.g., silicon oxide). This composite approach allows optimization of electrical insulation in specific regions while maintaining overall structural integrity and compatibility with standard semiconductor manufacturing processes.
3Quantity of substance
If gate electrodes are closely spaced to increase storage capacity, then data storage capacity increases, but electrical interference between gates increases
Solution Approach 1:
Spacer layers are introduced as intermediary structures between the contact plugs and the gate electrodes. These spacer layers, formed with specific materials and dimensions, provide electrical insulation and prevent direct contact between conductive elements, thereby reducing electrical interference between closely spaced gate electrodes while enabling increased data storage capacity through higher gate density.
Solution Approach 2:
The spacer layers continuously extend along the sidewalls of the contact plugs, providing uninterrupted electrical insulation. This continuous protective action ensures that even as gate electrodes are closely spaced to increase storage capacity, the electrical insulation remains effective throughout the entire interface region, preventing leakage and interference.
Data Source
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AI summary
A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.