3D Memory Contact Plug Layout for Deep Word Line Contacts
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Solution Overview
Problem
In semiconductor storage devices with three-dimensional memory cell arrays, forming high-density word line contacts is challenging due to the difficulty in penetrating contact holes deeply without piercing through shallow word lines, leading to issues with contact resistance and reliability.
Innovation Solution
The semiconductor storage device employs a stacked body structure with alternately layered conducting and insulating films, where contact plugs are arranged in a specific pattern to form equilateral triangles in the X-Y plane, reducing density and preventing overetching, allowing for deeper and more reliable contact formation without piercing through word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are formed at high density to decrease resistance, then contact resistance decreases, but contact holes cannot sufficiently penetrate to the required depth
Solution Approach 1:
The patent segments the contact hole formation process by creating multiple types of contact holes (first contact holes for word line contacts and second contact holes for bonding pads) with different depth requirements. This segmentation allows each contact hole type to be optimized independently, resolving the contradiction between high density and sufficient penetration depth.
Solution Approach 2:
The patent applies local quality by assigning different spatial arrangements and depth specifications to different contact hole regions. First contact holes are arranged with larger pitch for adequate penetration, while second contact holes are arranged with smaller pitch for high density. This local differentiation resolves the contradiction by allowing high density where needed without compromising penetration depth elsewhere.
2Reliability
If contact holes are formed to sufficient depth, then contact reliability improves, but shallow word line contacts are pierced through
Solution Approach 1:
The patent segments contact holes into different depth categories: first contact holes that terminate before piercing word lines, and second contact holes that extend deeper. This segmentation enables precise control over penetration depth, ensuring word line contacts are not damaged while achieving sufficient reliability for bonding pad connections.
Solution Approach 2:
The patent applies partial action by forming first contact holes to a depth that is sufficient for word line contact reliability but intentionally stops before the excessive depth that would pierce through the word lines. This controlled partial penetration resolves the contradiction between achieving adequate reliability and preventing damage.
3Ease of manufacture
If word line contacts and bonding pad contacts are formed simultaneously, then manufacturing process is simplified, but contact hole penetration control becomes difficult
Solution Approach 1:
The patent applies local quality by implementing different formation conditions for different contact hole types within the same manufacturing process. First contact holes use one set of parameters (larger pitch, controlled depth) while second contact holes use another set (smaller pitch, greater depth). This local differentiation maintains process simplicity while achieving precise depth control.
Solution Approach 2:
The patent segments the contact hole formation into distinct categories with different specifications, allowing simultaneous formation with different depth controls. By defining first and second contact holes with different pitch and depth requirements, the patent resolves the contradiction between process simplicity and depth control precision.
Data Source
AI summary
A semiconductor storage device according to the present embodiment includes a stacked body including a plurality of first conducting films and a plurality of first insulating films alternately stacked in a first direction. A plurality of columnar bodies each include a first semiconductor part extending in the first direction in the stacked body, and a first insulator part located between the first semiconductor part and the stacked body. A transistor is located in the first direction of the stacked body. A plurality of first conductors extend in the first direction and are connected to the transistor. Three adjacent ones of the first conductors are arranged to form an equilateral triangle in a first plane orthogonal to the first direction.