Memory Contact Plug Resistance Adjustment for Overcurrent Protection
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Solution Overview
Problem
Semiconductor memory devices face issues with damage due to excessive current when large currents are applied to memory cells, leading to reliability concerns and potential overcurrents in cells with shorter current paths.
Innovation Solution
The solution involves varying the resistance of contact plugs connected to memory cells, with those connected to shorter current paths having higher resistances to compensate for array wiring resistance differences, thereby preventing overcurrents by adjusting the resistance values of row and column contact plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged with different current path lengths, then memory cell density is improved, but current distribution becomes uneven causing overcurrent damage
Solution Approach 1:
The patent applies local quality by assigning different resistance values to different contact plugs based on their specific location and current path characteristics. Contact plugs connected to memory cells with shorter current paths are given higher resistance values, while those with longer paths receive lower resistance values. This localized customization of resistance compensates for the inherent unevenness in current path lengths, ensuring uniform current distribution across all memory cells while maintaining high memory cell density.
2Ease of manufacture
If contact plugs have uniform resistance, then manufacturing is simplified, but memory cells with shorter current paths receive excessive current
Solution Approach 1:
The patent implements parameter changes by varying the resistance value parameter of contact plugs based on their position in the memory array. Instead of using a uniform resistance value for all contact plugs, the invention assigns different resistance values according to the current path length characteristics of associated memory cells. This can be achieved through different material compositions, cross-sectional areas, or lengths of the contact plugs, thereby preventing overcurrent damage while maintaining manufacturing feasibility through systematic parameter adjustment.
3Speed
If current path length is reduced for faster operation, then speed is improved, but current density increases causing potential damage
Solution Approach 1:
The patent applies the counterweight principle by introducing additional resistance as a compensating factor against the reduced current path length. Memory cells with shorter current paths, which inherently have lower resistance and thus higher current density, are paired with contact plugs that have higher resistance values. This additional resistance acts as a counterbalancing element that offsets the low path resistance, thereby reducing current density to safe levels while preserving the speed advantage of the short current paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating characteristics and reliability of memory cells by ensuring consistent current distribution, preventing damage from overcurrents and improving the integration and performance of memory elements in semiconductor devices.
Implementation Method 1
processing the first conductive plug to increase a resistance of the first conductive plug to a value higher than a resistance of the second conductive plug
Data Source
AI summary
An electronic device includes a semiconductor memory comprising row lines, column lines, memory cells, and a plurality of contact plugs including row contact plugs respectively coupled to the row lines and column contact plugs respectively coupled to the column lines. Each memory cell is coupled to a row line and a column line, and has a current path comprising a portion of that row line and a portion of that column line. First and second contact plug are respectively coupled to first and second memory cells respectively having first and second current paths. A resistance of the first current path is lower than a resistance of the second current path, and a resistance of the first contact plug is increased relative to a resistance of the second contact plug to offset the lower resistance of the first current path.