Variable Resistance Memory Contact Plug Resistance Distribution
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Solution Overview
Problem
Variable resistance memory devices face operational reliability issues due to excessive current flow when located closer to selection circuits, leading to deteriorated characteristics and durability, as current varies based on position within the memory cell array.
Innovation Solution
The memory device incorporates contact plugs with adjustable resistance depending on location, and a layout of conductive lines with varying widths and orientations to manage current flow effectively, ensuring balanced signal delay compensation across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are located closer to selection circuits to increase integration density, then device area is reduced, but current flow becomes excessive leading to deteriorated characteristics and reliability
Solution Approach 1:
The patent applies local quality by configuring different contact plug resistances based on their location within the memory device. Contact plugs closer to the selection circuit have higher resistance values, while those farther away have lower resistance values. This spatial variation in electrical properties compensates for the decreased signal delay near the selection circuit, balancing the operational characteristics across all memory cells regardless of their position.
2Reliability
If memory cells are located farther from selection circuits to reduce current flow, then operational reliability improves, but signal delay increases and device area expands
Solution Approach 1:
The patent implements local quality by assigning different resistance values to contact plugs based on their spatial position. Memory cells farther from the selection circuit are paired with contact plugs having lower resistance to compensate for the increased signal delay and current flow path length, thereby maintaining uniform operational characteristics across the entire memory array.
3Ease of manufacture
If uniform contact plug resistance is used across all memory cells, then manufacturing complexity is reduced, but current flow varies by position leading to deteriorated characteristics
Solution Approach 1:
The patent applies local quality by configuring different contact plug resistances based on their location within the memory device. Contact plugs closer to the selection circuit have higher resistance values, while those farther away have lower resistance values. This spatial variation in electrical properties compensates for the decreased signal delay near the selection circuit, balancing the operational characteristics across all memory cells regardless of their position.
Data Source
AI summary
A memory device is provided. A memory device includes a memory cell array having variable resistance memory cells that are coupled to and disposed between first conductive lines extending in a first direction and second conductive lines crossing the first conductive lines, and a selection circuit configured to select the first conductive lines. The second conductive lines include straight conductive lines extending in a second direction that crosses the first direction, and first bending conductive lines spaced apart from the selection circuit by the straight conductive lines, the first bending conductive lines extending parallel with each other, and having an L shape.


