Variable Resistance Memory Contact Plug Vertical Integration
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Solution Overview
Problem
The integration degree of variable resistance memory devices with a cell over periphery (COP) structure is limited due to the small size of contact plugs connecting transistors to word lines and bit lines, which can lead to issues such as electromigration and bias temperature stress, especially when these plugs are small in size.
Innovation Solution
The design includes a variable resistance memory device with a substrate having a cell region and a peripheral circuit region, featuring transistors and conductive lines with contact plugs that extend vertically to connect to transistors without overlapping memory units, using materials like tungsten to reduce electromigration and bias temperature stress, and are structured to avoid overlapping with memory units, allowing for improved electrical connectivity and reduced plug size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact plugs are made small to increase integration density, then integration degree is improved, but electromigration and bias temperature stress increase
Solution Approach 1:
The contact plug structure transitions from a conventional planar configuration to a three-dimensional structure that extends vertically from the substrate through the insulating layer to contact the conductive line. This vertical extension in the third dimension allows for effective electrical connection while maintaining a compact footprint in the planar direction, thereby achieving high integration density without compromising reliability
Solution Approach 2:
The contact plug is nested within the vertical stack of the memory device structure, extending from the substrate upward through the insulating layer to contact the conductive line. This nested configuration allows the contact plug to efficiently utilize the vertical space, enabling small plug dimensions while maintaining effective electrical connectivity and reducing planar footprint for higher integration
2Productivity
If contact plugs are made small to increase integration degree, then integration degree is improved, but bias temperature stress increases
Solution Approach 1:
The contact plug extends vertically in the third dimension from the substrate through the insulating layer to contact the conductive line. This vertical configuration reduces the planar footprint while maintaining effective electrical connection, achieving high integration degree without excessive miniaturization that would cause bias temperature stress
Solution Approach 2:
The insulating layer acts as an intermediary between the substrate and the conductive line, with the contact plug extending through it. This intermediate structure provides a controlled pathway for electrical connection while maintaining proper spacing and reducing stress concentration, enabling small contact plugs without compromising device reliability
3Productivity
If contact plugs are made small, then integration density is improved, but electrical connectivity may be compromised
Solution Approach 1:
The contact plug structure utilizes the vertical dimension by extending from the substrate upward through the insulating layer to contact the conductive line. This vertical extension provides an effective electrical connection pathway while minimizing the planar footprint, thereby achieving high integration density without compromising electrical connectivity
Solution Approach 2:
The contact plug is nested vertically within the device stack, extending from the substrate through the insulating layer to contact the conductive line. This nested configuration enables efficient electrical connection with minimal planar space, achieving both high integration density and reliable electrical connectivity
Data Source
AI summary
A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.