3D Memory Contact Region Reduction via Vertical Electrode Nesting
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Solution Overview
Problem
In three-dimensional memory devices, the increasing number of stacked wiring layers leads to a larger contact region, which is undesirable as it increases the chip area, and the number of contact electrodes, necessitating a reduction in the contact region area to maintain efficiency.
Innovation Solution
The memory device employs a configuration where conductive layers are arranged stepwise in one direction, with specific electrodes connected to these layers, and a region without the second conductive layer is provided between certain electrodes, reducing the area required for contact electrodes and thus the chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked wiring layers is increased to increase integration, then the integration density is improved, but the contact region area increases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of contact electrodes to a three-dimensional stacked arrangement. Contact electrodes are positioned at different heights (z-direction) corresponding to different wiring layers, allowing vertical integration rather than horizontal expansion. This dimensional change enables multiple contact electrodes to be arranged in the vertical direction, reducing the horizontal footprint of the contact region while maintaining the ability to connect to multiple wiring layers.
Solution Approach 2:
The patent implements a nested structure where contact electrodes are positioned within and between stacked wiring layers. The contact electrodes are embedded in the insulating film and extend vertically to contact multiple conductive layers at different levels, creating a nested configuration where electrodes are contained within the vertical stack of wiring layers. This nesting allows efficient use of vertical space to reduce the horizontal contact region area.
2Adaptability or versatility
If the number of contact electrodes is increased to connect to more wiring layers, then the connectivity is improved, but the contact region area increases
Solution Approach 1:
The patent resolves this contradiction by arranging contact electrodes in the vertical dimension rather than spreading them horizontally. Multiple contact electrodes can connect to different wiring layers by extending vertically through the insulating film, enabling high connectivity without increasing the horizontal contact region area. The electrodes are positioned at different z-heights to match different wiring layer levels.
Solution Approach 2:
The patent segments the contact electrode structure into multiple discrete electrodes, each connecting to specific wiring layers. Rather than using a single large contact region, the structure is divided into multiple smaller contact electrodes positioned at different vertical levels. Each electrode can be independently sized and positioned, allowing optimized connectivity with minimal total contact area.
Data Source
AI summary
A memory device according to an embodiment includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer parallel to a first direction and a second direction perpendicular to the first direction, and stacked in a third direction perpendicular to the first direction; a first, electrode connected to the first conductive layer; a second electrode connected to the second conductive layer; a third electrode connected to the third conductive layer; and a fourth electrode connected to the fourth conductive layer. The third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode. The fourth conductive layer is not provided between the second electrode and the third electrode. A region without the second conductive layer is provided between the second electrode and the third electrode.