3D Nonvolatile Memory Contact Stop Layout for Reliable Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high performance, small size, and low cost while maintaining operation reliability, particularly in three-dimensional configurations where vertical integration of memory cells is sought.
Innovation Solution
A nonvolatile memory device design featuring a peripheral circuit structure with a cell array structure that includes a common source line layer, buffer insulating layers, and a staircase-shaped gate electrode configuration, along with contact stop layers and channel structures, which enhances electrical connectivity and structural stability through metal-oxide hybrid bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional vertical integration is implemented to increase memory density, then storage capacity is improved, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The memory device is divided into multiple stacked layers including first and second substrates, intermediate layers, and distinct functional regions (memory cell region, transistor region, contact region). This segmentation allows each layer to be manufactured and tested separately before final assembly, reducing overall manufacturing complexity while achieving high storage capacity through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional memory architecture to three-dimensional vertical stacking. Multiple memory layers are stacked in the vertical direction with each layer containing memory cells, transistors, and contact structures. This dimensional change dramatically increases storage capacity without proportionally increasing manufacturing complexity, as standard planar fabrication processes can be applied to each layer.
2Quantity of substance
If three-dimensional vertical integration is implemented to increase memory density, then storage capacity is improved, but operation reliability deteriorates
Solution Approach 1:
An intermediate layer is positioned between the first and second substrates to provide mechanical cushioning and stress relief. This intermediate layer prevents crack propagation and absorbs thermal expansion differences, thereby maintaining operation reliability in the stacked three-dimensional structure while enabling increased storage capacity.
Solution Approach 2:
Different regions of the stacked structure are optimized with locally appropriate properties. The intermediate layer has different material composition and mechanical properties compared to the substrate and memory cell layers. This local quality optimization ensures that each region performs its specific function (mechanical support, electrical isolation, data storage) while maintaining overall structural reliability.
3Ease of manufacture
If conventional planar structure is used, then manufacturing is simple, but memory density and performance are limited
Solution Approach 1:
The patent employs vertical stacking in the third dimension to achieve high memory density. Multiple layers are stacked vertically with each layer containing complete functional units (memory cells, transistors, contacts). This allows conventional planar manufacturing processes to be applied repeatedly to each layer, maintaining manufacturing simplicity while dramatically increasing overall memory density.
Solution Approach 2:
The memory device is segmented into multiple identical or similar layers that can be manufactured using the same process steps. Each layer contains memory cells, transistors, and contact structures that are fabricated using standard planar processes, then stacked vertically. This segmentation enables high density without requiring new manufacturing techniques.
Data Source
AI summary
A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit and a first insulating structure covering the peripheral circuit and a cell array structure bonded to the peripheral circuit structure and including a cell region and a connection region, wherein the cell array structure includes a common source line layer, a buffer insulating layer on the common source line layer, a plurality of contact stop layers buried in the buffer insulating layer, a cell stack which includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on the buffer insulating layer, a plurality of cell channel structures extending to the common source line layer by passing through the cell stack, a plurality of contact structures each connected to one or more of the plurality of gate electrodes, and a second insulating structure covering the cell stack.