Memory Contact Structures for Tight-Pitch Line Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microelectronic device designs face challenges in reducing the size and improving the performance of memory devices, particularly due to limitations in processing conditions and the configuration of control logic devices within the base control logic structure.
Innovation Solution
The proposed solution involves a microelectronic device structure with a first microelectronic device structure attached to a second microelectronic device structure, where the first structure includes memory arrays and the second structure includes control logic devices vertically overlying the memory cells, with socket regions for coupling components to BEOL structures. The contact structures in the digit and word line exit regions have tapered sidewalls to maintain a smaller pitch for electrical connections and a larger pitch for alignment and misregistration compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of digit and word lines is reduced to increase integration density, then the level of integration is improved, but the risk of electrical shorting between adjacent lines increases
Solution Approach 1:
The contact structure is divided into multiple discrete contact regions along the digit line and word line exits. Each contact region is separated by isolation material, creating individual electrical connection points that prevent current leakage between adjacent lines while maintaining tight pitch.
Solution Approach 2:
An isolation material layer is introduced as an intermediary between adjacent digit lines and word lines at their exit regions. This intermediate layer electrically insulates the closely-spaced conductors, preventing short circuits while allowing the lines to maintain a small pitch for high density.
2Productivity
If the separation distance between neighboring features is reduced to increase density, then the integration level is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The contact structures are formed with predetermined dimensions and spacing before the attachment process. The isolation material is deposited to a controlled thickness that pre-establishes the minimum safe distance between adjacent conductors, compensating for potential alignment variations during subsequent bonding operations.
Solution Approach 2:
The isolation material layer acts as a cushion or buffer between adjacent digit lines and word lines. This intermediate layer provides a safety margin that absorbs alignment errors and registration mismatches during device attachment, preventing electrical shorts even when features are not perfectly aligned.
3Productivity
If control logic devices are increased in quantity to improve performance, then the device functionality is improved, but the horizontal footprint of the memory device increases
Solution Approach 1:
Control logic devices are positioned in the vertical dimension above the memory array rather than being distributed horizontally across the chip. This vertical stacking allows multiple control logic devices to coexist without increasing the horizontal footprint, maintaining high device performance while preserving compact chip area.
Solution Approach 2:
The microelectronic device structure employs a nested arrangement where control logic devices are vertically stacked over the memory array region. This nesting approach allows the control logic to be integrated within the same horizontal footprint as the memory cells, maximizing space utilization and maintaining small device dimensions.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.