Semiconductor Memory Device Continuous Verification Method
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Solution Overview
Problem
Semiconductor memory devices, particularly nonvolatile flash memory, face limitations in program operation speed due to the need for frequent bit line precharge and discharge operations during verification processes, which slow down the overall programming process.
Innovation Solution
The semiconductor memory device employs a method where two verification operations are performed continuously using different verification voltages, allowing the skipping of bit line discharge and precharge operations between these verifications, and adjusts program pulses by incrementing previous pulses by a step voltage and twice the step voltage to ensure complete programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequent bit line precharge and discharge operations are performed during verification processes, then verification accuracy is improved, but program operation speed deteriorates
Solution Approach 1:
The verification process is segmented into multiple verification operations, each using different verification voltages. This allows the bit line to be discharged and precharged selectively between verifications rather than continuously, improving speed while maintaining accuracy through multiple discrete check points
Solution Approach 2:
Two verification operations are performed continuously without interruption between them, eliminating idle time and maintaining continuous useful action. The bit line discharge and precharge operations are optimized to occur only when necessary, keeping the verification process continuous and efficient
2Manufacturing precision
If multiple verification operations are performed with different verification voltages, then programming completeness is improved, but operation time increases
Solution Approach 1:
The bit line is precharged to a specific voltage level before the first verification operation, and the discharge and precharge operations are performed in advance of the second verification. This preliminary preparation ensures that each verification starts with optimal conditions, improving programming completeness while minimizing total operation time
Solution Approach 2:
Verification operations are performed periodically at different voltage levels (first verification voltage, then second verification voltage). This periodic verification approach ensures complete programming by checking at multiple threshold levels while maintaining a rhythmic, efficient operation pattern that minimizes delays
Data Source
AI summary
Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.