Memory Control Logic for Address Redirection in Damaged Regions

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Solution Overview

Problem

The memory industry faces challenges in achieving further breakthroughs in wafer yield due to slight defects making entire memory chips unusable, leading to resource wastage and environmental issues, without the use of backup components or error correction codes.

Innovation Solution

A memory-control logic and method that utilize a one-time-programmable (OTP) memory array, array-control circuit, and address-redirecting circuit to program and redirect memory addresses, effectively rerouting access from damaged regions to good regions within a memory-cell array, utilizing redundant regions to replace damaged ones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If no backup components or error correction codes are used, then device complexity is reduced, but reliability deteriorates due to slight defects making entire memory chips unusable

Engineering Contradiction:
Improvedevice complexityVSAvoidreliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The memory array is divided into multiple regions (first region, second region, third region, fourth region), allowing localized failure isolation. When a defect occurs in one region, other regions can still function, thereby improving reliability without requiring complex backup components or error correction codes across the entire chip.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the memory array are assigned different functions or characteristics. The patent applies region-specific failure flags and redirecting mapping tables, allowing each region to be independently managed and tested, improving overall system reliability while maintaining relatively simple device architecture.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If the entire memory chip is made unusable due to slight defects, then manufacturing precision requirements are simplified, but productivity deteriorates due to resource wastage

Engineering Contradiction:
Improvemanufacturing precisionVSAvoidproductivity
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent performs preliminary testing and classification of memory regions during manufacturing, identifying good regions and damaged regions in advance. By pre-determining which regions are functional and which are defective, the system can redirect addresses to good regions before the chip is deployed, thereby improving productivity and reducing resource wastage without requiring extremely high manufacturing precision.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent discards (marks as unusable) only the specific damaged regions rather than the entire memory chip. By recovering and utilizing the good regions through address redirection, the system maximizes the usable portion of each chip, thereby improving productivity and reducing waste without needing to discard entire chips due to minor defects.

Inventive Principle:
Principle #34Discarding and recovering

3Adaptability or versatility

If address redirection is implemented dynamically, then adaptability is improved, but device complexity increases due to additional control circuits

Engineering Contradiction:
ImproveadaptabilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic address redirection by allowing the redirecting mapping table to be programmed with different region mappings based on detected failure patterns. The system can adaptively redirect addresses to different good regions depending on which regions are damaged, improving adaptability while using a relatively simple control circuit structure that updates mapping tables rather than requiring complex real-time control logic.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11860671B2Memory-control logic and method of redirecting memory addresses
Publication Date: 2024.01.02 WINBOND ELECTRONICS CORP
  • US11860671B2 patent drawing
  • US11860671B2 patent drawing
  • US11860671B2 patent drawing

AI summary

A memory-control logic, disposed in a memory circuit, is provided. The memory circuit includes a memory-cell array that is divided into a plurality of regions that include a damaged region. The memory-control logic includes a one-time-programmable (OTP) memory array, an array-control circuit, and an address-redirecting circuit. The array-control circuit programs a memory-size type of the memory-cell array, a region-failure flag corresponding to each region, and a redirecting mapping table corresponding to each region in the OTP memory array. The array-control circuit programs the redirecting mapping table corresponding to each region according to the memory-size type to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions. The address-redirecting circuit converts the address signal into a first redirected address signal according to the redirecting mapping table corresponding to each region, and inputs the redirected address signal into the memory-cell array.