Memory Control Circuit Adjustable Data Delay Phase Difference
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Solution Overview
Problem
In DDR RAM systems, when the frequency of the clock signal increases and signal delays within the circuit system are not properly corrected, the data strobe signal may not comply with specifications, leading to incorrect writing of data into memory cells due to an unsuitable time interval (TDQSS).
Innovation Solution
A memory control circuit and method that includes a phase detection module to detect the phase difference between the data strobe and clock signals, generating control signals to adjust the delay of the odd/even data separation signal, ensuring proper alignment and writing into memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal is increased to improve data accessing speed, then the data accessing speed is improved, but the phase difference between the data strobe signal and clock signal increases causing timing violation
Solution Approach 1:
The patent implements dynamic delay adjustment in the data strobe signal path based on detected phase difference. The delay amount is variable and adapts to different operating conditions, allowing the system to maintain timing compliance across a range of clock frequencies. This dynamic adjustment resolves the contradiction by making the delay characteristic adjustable rather than fixed.
Solution Approach 2:
The patent changes the delay parameter of the data strobe signal to compensate for phase differences caused by increased clock frequency. By adjusting the delay time based on phase detection results, the system maintains proper timing alignment between the data strobe signal and clock signal, thus preserving reliability while allowing higher operating speeds.
2Productivity
If the clock signal frequency is increased to double data rate operation, then productivity is improved, but signal delay correction becomes insufficient causing incorrect data writing
Solution Approach 1:
The patent employs a feedback mechanism where the phase difference between the data strobe signal and clock signal is detected and used to control the delay adjustment. This closed-loop feedback ensures that the data strobe signal timing is continuously optimized to maintain proper alignment with the clock signal, preventing incorrect data writing while sustaining high throughput.
Solution Approach 2:
The patent replaces fixed mechanical delay paths with electronically controllable delay elements that can be dynamically adjusted based on phase detection. This substitution allows precise control of signal timing through electrical parameters rather than fixed physical path lengths, enabling accurate delay correction at higher data rates.
3Ease of operation
If no delay adjustment is applied to maintain simple circuit operation, then ease of operation is maintained, but the data strobe signal fails to meet specification causing writing errors
Solution Approach 1:
The patent implements a self-adjusting system where the circuit automatically detects phase differences and adjusts its own delay parameters without external intervention. The phase detection module continuously monitors the timing relationship and the control module automatically modifies the delay, allowing the system to self-correct timing issues while maintaining reliable data writing.
Solution Approach 2:
The patent combines the phase detection function and delay adjustment control into an integrated timing control mechanism. By merging these functions, the system achieves automatic timing compensation without requiring separate complex control circuits, thus maintaining operational simplicity while improving reliability through adaptive delay adjustment.
Data Source
AI summary
A memory control circuit includes: a phase detection module for detecting a phase difference between a data strobe signal and a clock signal; a control module, coupled to the phase detection module, for generating a set of control signals according to the phase difference, where the set of control signals correspond to the phase difference; a latch module for latching write data carried by a data signal according to rising/falling edges of the data strobe signal; an odd/even data separator, coupled to the latch module, for performing odd/even data separation on the write data to generate a data separation signal carrying odd/even data corresponding to the write data; and an adjustable delay line module, coupled to the odd/even data separator and the control module, for adjusting the odd/even data's delay according to the control signals, where the delay amount of the odd/even data corresponds to the control signals.