Memory Device Control Logic for Program Algorithm Selection

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Solution Overview

Problem

Nonvolatile memory devices face challenges in efficiently performing program operations due to limitations in read and write speeds and the need for optimized voltage conditions for different program algorithms, which can lead to increased operation times and resource usage.

Innovation Solution

A memory device with a control logic that stores multiple program algorithms and operation information in registers, allowing selection of the appropriate algorithm based on the program target page address, enabling efficient program operations by varying the step voltage and verify operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple program algorithms with different voltage conditions are stored in registers, then program operation efficiency is improved, but register capacity requirements increase

Engineering Contradiction:
Improveprogram operation efficiencyVSAvoidregister capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent divides program algorithms into multiple groups based on voltage conditions (first group with first voltage condition, second group with second voltage condition). This segmentation allows the memory device to select appropriate algorithms for different program operation scenarios, improving efficiency without requiring all algorithms to be stored simultaneously in a single large register structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic selection of program algorithms based on voltage conditions and page addresses. The control logic dynamically chooses between different voltage conditions and corresponding algorithms during operation, allowing the system to adapt to different program requirements without permanently storing all possible algorithm variations.

Inventive Principle:
Principle #15Dynamics

2Speed

If voltage conditions are optimized for different program algorithms, then program operation speed is improved, but operation complexity increases

Engineering Contradiction:
Improveprogram operation speedVSAvoidoperation complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent applies different voltage conditions to different groups of program algorithms based on specific program operation characteristics. By matching voltage conditions locally to algorithm requirements rather than using a uniform voltage approach, the system achieves optimized speeds for each algorithm type while managing complexity through structured grouping.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes voltage parameters based on the selected program algorithm group. By varying the voltage condition parameter according to the algorithm being executed, the system optimizes program operation speed for different scenarios while the control logic manages the parameter changes to prevent excessive complexity.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If program algorithms are selected based on page address, then program operation precision is improved, but control complexity increases

Engineering Contradiction:
Improveprogram operation precisionVSAvoidcontrol complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent pre-organizes program algorithms into groups associated with specific page address ranges before operation begins. This preliminary classification allows the control logic to quickly determine the appropriate voltage condition and algorithm group based on the incoming page address without requiring complex real-time analysis, thus improving precision while managing control complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10846236B2Memory device and method of operating the same
Publication Date: 2020.11.24 SK HYNIX INC
  • US10846236B2 patent drawing
  • US10846236B2 patent drawing
  • US10846236B2 patent drawing

AI summary

A memory device and a method of operating the same. The memory device may include a memory block including a plurality of pages, and a control logic configured to include at least one register in which a plurality of program algorithms and a plurality of pieces of operation information are stored, select any one of the program algorithms in response to an address of a program target page, among the pages, and perform a program operation on the program target page based on the selected program algorithm and operation information corresponding to the selected program algorithm.