Memory Control Device Bandwidth Extension via Segmentation
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Solution Overview
Problem
Conventional memory control methods fail to effectively extend memory bandwidth while minimizing invalid data transfer and maintaining high access efficiency, especially when using high-speed DRAMs, due to increased minimum access units and unnecessary data transfers during image processing with small and non-continuous access patterns.
Innovation Solution
A memory control device that divides memory access requests into commands for multiple memory units, allowing simultaneous access with identical or different physical addresses, and manages data transfer to minimize invalid data and reduce the minimum access unit, thereby extending memory bandwidth without increasing the minimum access unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bus width is extended or high-speed DRAM is used to extend memory bandwidth, then memory bandwidth is improved, but the minimum access unit increases and invalid data transfer increases
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices (first memory device and second memory device), each with its own command interface and data interface. This segmentation allows the system to access multiple memory devices simultaneously with different burst lengths, thereby extending effective memory bandwidth without increasing the minimum access unit for individual devices. The master can issue commands to both memory devices in parallel, achieving higher throughput while maintaining small access units for each device.
2Productivity
If the bus width is extended or high-speed DRAM is used to extend memory bandwidth, then memory bandwidth is improved, but the minimum access unit increases
Solution Approach 1:
The patent segments the memory system into multiple independent memory devices, each maintaining its own minimum access unit characteristics. By accessing multiple segmented devices simultaneously with different burst lengths, the system achieves extended bandwidth without any single device requiring a increased minimum access unit. Each memory device operates independently with its native access unit size.
Solution Approach 2:
The patent enables dynamic configuration of burst lengths for different memory devices based on access patterns. The system can adaptively set the first memory device to a first burst length and the second memory device to a second burst length, allowing flexible adjustment of access parameters to optimize performance without being constrained by a fixed increased minimum access unit.
3Productivity
If bank interleaving is performed to mask inaccessible period, then access efficiency is improved, but transfer size per access must be increased
Solution Approach 1:
The patent divides the memory system into multiple independent memory devices that can be accessed simultaneously. Instead of using bank interleaving within a single memory device which requires increased transfer size, the system segments access across multiple devices, allowing small transfer sizes to each device while achieving high access efficiency through parallel operations.
Solution Approach 2:
The patent transitions from temporal masking (bank interleaving in time) to spatial parallelism (simultaneous access to multiple memory devices). By adding the dimension of multiple independently accessible memory devices, the system achieves access efficiency improvement without increasing transfer size, as each device handles small transfers concurrently rather than sequentially masking latency.
Data Source
AI summary
The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.