Memory Control Circuit for Nonvolatile Cache Power Management
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Solution Overview
Problem
Current processor systems face performance degradation due to the need for continuous power supply to cache memories, as data in volatile cache memories is lost when power is cut off, leading to longer read times and increased power consumption.
Innovation Solution
A memory control circuit that determines periods of inactivity in non-volatile cache memories and controls power cut-off timing using a read request counter and power-supply controller, allowing for early power cut-off without affecting processor operation, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is continuously supplied to volatile cache memories to prevent data loss, then data reliability is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic power supply control by monitoring cache access requests over time intervals. The power supply controller periodically evaluates whether to supply power to cache memories based on access frequency, enabling the system to switch between power-saving and performance modes dynamically rather than maintaining continuous power supply.
Solution Approach 2:
The memory control circuit includes a request determination circuit that automatically monitors cache access patterns and determines power supply timing without external intervention. The system self-regulates power consumption by having the memory control circuit independently assess whether cache access requests have occurred and control power supply accordingly, eliminating the need for continuous external power management.
2Use of energy by moving object
If power is cut off to cache memories to reduce power consumption, then power efficiency improves, but data is lost requiring re-read from higher level memory
Solution Approach 1:
The system performs preliminary actions by pre-loading data into cache memories when access requests are anticipated or detected. The request determination circuit monitors for incoming access requests and triggers power supply or data retention actions before actual cache access is needed, ensuring data is ready when required and minimizing re-read delays.
Solution Approach 2:
The patent implements feedback mechanisms where the memory control circuit continuously monitors cache access requests and uses this information to dynamically control power supply. The system feeds back access pattern information to the power supply controller, which adjusts power supply timing based on actual usage, thereby optimizing the balance between power savings and data availability.
3Adaptability or versatility
If power management is performed by operating system, then system-level power control is achieved, but processor cannot independently manage cache memory power
Solution Approach 1:
The patent segments power management control by separating cache memory power control from general system power management. The memory control circuit includes dedicated request determination circuitry that independently monitors cache access requests and controls power supply to cache memories separately from other system components, enabling processor-level power management autonomy.
Solution Approach 2:
The memory control circuit acts as an intermediary between the processor and power supply system. It receives access request information from the processor, determines appropriate power supply timing, and controls power delivery to cache memories, thereby enabling the processor to independently manage cache power without direct involvement of the operating system or other system-level controllers.
Data Source
AI summary
A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.