Memory Device Control Circuit for Cross-Point Array Reliability
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Solution Overview
Problem
Current memory devices with cross-point memory cell arrays face challenges in efficiently performing reinforcement learning due to the risk of memory cell damage from frequent write operations, which can lead to inaccurate read results and reduced reliability.
Innovation Solution
The memory device employs a control circuit that manages write operations by changing the method of the penalty process based on the progress of learning, executing a second write operation that increases the resistance value only for selected memory cells in early trial processes and switching to a first write operation that lowers the resistance value for non-selected cells in subsequent processes, thereby reducing stress on memory cells and improving data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If frequent write operations are performed in cross-point memory cell arrays during reinforcement learning, then learning speed and adaptability are improved, but memory cell reliability deteriorates due to damage from excessive write operations
Solution Approach 1:
The patent dynamically adjusts the penalty process method based on learning progress. In early trial processes, it applies a second penalty process (increasing resistance) only to selected memory cells. In subsequent processes, it switches to a first penalty process (decreasing resistance) for non-selected cells. This dynamic adaptation allows frequent write operations for learning speed while managing memory cell stress to maintain reliability.
Solution Approach 2:
The patent changes the resistance value parameter of memory cells based on selection status and learning stage. Selected cells have their resistance increased, while non-selected cells have resistance decreased in later stages. This parameter manipulation enables the system to perform reinforcement learning with frequent writes while controlling overall memory cell degradation through selective parameter adjustment.
2Reliability
If the number of write operations is reduced to protect memory cells, then memory cell reliability is improved, but reinforcement learning time increases
Solution Approach 1:
The patent segments the memory cell array into selected and non-selected portions, and further divides penalty processes into early stage (second penalty) and subsequent stage (first penalty). This segmentation allows different write strategies to be applied to different cell groups at different times, enabling frequent enough writes to maintain learning speed while limiting total writes to protect reliability.
Solution Approach 2:
The patent implements periodic switching between different penalty processes based on learning progress. The second penalty process (increase resistance) is applied in early trials, then transitions to the first penalty process (decrease resistance) in subsequent trials. This periodic action pattern allows the system to balance learning efficiency with memory cell protection over time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of data storage and shortens the time required for reinforcement learning without significantly deteriorating learning performance, by minimizing the number of write operations and reducing the risk of memory cell damage.
Implementation Method 1
executing a second write operation that increases the resistance value only for selected memory cells in early trial processes and switching to a first write operation that lowers the resistance value for non-selected cells in subsequent processes
Data Source
AI summary
A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.