Memory Control Circuit Reduces Crosstalk in 2T0C Arrays
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Solution Overview
Problem
Traditional dynamic random access memories (DRAMs) face challenges due to leakage in transistors, requiring frequent data refresh and increasing power consumption. Metal oxide transistors offer lower leakage but still face issues with crosstalk and current sharing in 2T0C memory arrays.
Innovation Solution
The implementation of a memory system with a control circuit that manages voltage transmission during pre-processing, pre-charging, and read-sensing stages to cut off the second transistor in each memory cell, thereby reducing crosstalk and improving data reading reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional silicon-based MOSFETs are used in memory cells, then the memory can operate with conventional transistors, but the transistor leakage is high requiring frequent refresh operations which increases power consumption
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional silicon-based MOSFET to metal oxide semiconductor TFT, fundamentally altering the electrical characteristics to achieve lower leakage current and reduced refresh requirements
Solution Approach 2:
The patent adopts the proven 2T0C memory cell architecture design and applies it to metal oxide semiconductor technology, copying the structural configuration while leveraging the superior electrical properties of the new transistor type
2Loss of energy
If metal oxide TFTs are used to replace silicon-based MOSFETs, then leakage current is reduced and refresh frequency can be lowered, but crosstalk and current sharing issues arise in 2T0C memory arrays
Solution Approach 1:
The patent applies preliminary actions by pre-charging bitlines and pre-conditioning wordlines before actual read/write operations to prevent crosstalk and ensure proper voltage levels, addressing interference issues before they affect data integrity
Solution Approach 2:
The patent introduces control circuits as intermediary components that manage voltage distribution and timing between wordlines and bitlines, mediating the interaction to prevent direct crosstalk while maintaining efficient operation
3Reliability
If frequent refresh operations are performed to maintain data in traditional DRAM, then data retention is maintained, but power consumption significantly increases
Solution Approach 1:
The patent changes the transistor material parameter to achieve inherently lower leakage current, which directly extends data retention time without requiring frequent refresh operations, thereby reducing power consumption
Data Source
AI summary
Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.