Memory Control Circuit Unit Decoding Error Evaluation
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Solution Overview
Problem
Traditional encoding/decoding technologies for rewritable non-volatile memory modules operate independently for block codes and single-page encoding/decoding, lacking an effective method to improve decoding capability based on error evaluation information across physical units.
Innovation Solution
A decoding method and memory control circuit unit that perform single-frame decoding on data frames from physical units, utilizing error evaluation information to obtain reliability information and enhance decoding capability, switching to multi-frame decoding when necessary to correct errors across multiple frames.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional independent block code decoding and single-page decoding are used, then the decoding process is simple and independent, but the decoding capability cannot be improved based on error evaluation information across physical units
Solution Approach 1:
The patent merges independent block code decoding and single-page decoding into a unified decoding architecture. The memory control circuit unit integrates error evaluation information from multiple physical units and applies it across different decoding contexts, allowing reliability information to be shared and utilized systematically rather than in isolation.
Solution Approach 2:
The patent implements feedback mechanisms where error evaluation information from initial decoding attempts is fed back into the decoding process. The memory control circuit unit uses this feedback to adjust reliability information and perform subsequent decoding operations with improved parameters, creating a closed-loop system that continuously refines decoding performance.
2Reliability
If error evaluation information from multiple physical units is utilized to improve decoding, then decoding success rate increases, but the processing time and complexity increase
Solution Approach 1:
The patent performs preliminary error evaluation on data frames from multiple physical units before the main decoding operation. The memory control circuit unit assesses error conditions in advance and prepares reliability information that guides subsequent decoding, preventing wasted processing time on obviously problematic data and enabling more efficient error correction.
Solution Approach 2:
The patent employs dynamic decoding strategies where the memory control circuit unit adjusts decoding parameters based on real-time error evaluation results. When error rates are low, simpler decoding paths are taken; when errors are detected, more robust decoding methods are activated, creating a dynamic response that optimizes processing time across different error conditions.
Data Source
AI summary
A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: respectively performing a single-frame decoding on a plurality of first data frames read from a physical unit set, the physical unit set contains a plurality of first physical units in a rewritable non-volatile memory module; in response to an entire decoding result of the first data frames meeting a first condition, obtaining error evaluation information related to the physical unit set, and the error evaluation information reflects a bit error status of the physical unit set; obtaining reliability information according to the error evaluation information; and performing the single-frame decoding on a second data frame read from one of the first physical units according to the reliability information.