Memory Control Circuit Unit Dynamic Read Voltage Selection

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Solution Overview

Problem

Rewritable non-volatile memory modules, especially those with three-dimensional memory cell arrays, face challenges in maintaining data accuracy due to charge loss, leading to reading errors, which can result in decoding failures when multiple errors occur.

Innovation Solution

A decoding method that uses multiple read voltage levels based on the usage state of memory cells to accurately obtain and combine bits, increasing the decoding success rate by distinguishing between different storage states within the memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single read voltage level is used to read memory cells, then the reading process is simple and fast, but reading errors occur due to charge loss in memory cells

Engineering Contradiction:
Improvereading accuracyVSAvoidread process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the read voltage level adjustable rather than fixed. The memory control circuit unit dynamically selects between first and second read voltage levels based on the usage state of memory cells. This dynamic adjustment allows the system to adapt to different charge loss conditions, improving reading accuracy while managing complexity through automated voltage selection based on memory cell usage patterns.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter by using multiple read voltage levels (first read voltage level and second read voltage level) instead of a single fixed voltage. The memory control circuit unit selects different voltage levels according to the usage state of memory cells, thereby compensating for charge loss effects and improving reading reliability without requiring complex additional hardware.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple read voltage levels are used to compensate for charge loss, then reading accuracy improves, but the read process becomes more complex and time-consuming

Engineering Contradiction:
Improvedecoding success rateVSAvoidread time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-determining the usage state of memory cells before the actual read operation. The memory control circuit unit uses the usage state information to pre-select the appropriate read voltage level, so that when the read operation occurs, the correct voltage is already chosen. This preliminary preparation avoids the need for multiple sequential read attempts, thereby improving decoding success rate while minimizing additional time consumption.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If memory cells are read using a fixed voltage level, then the read operation is fast, but errors occur due to varying storage states of memory cells

Engineering Contradiction:
Improvebit reading accuracyVSAvoidread efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent applies local quality by tailoring the read voltage level to the specific usage state of memory cells. Instead of using a uniform voltage for all memory cells, the system applies different voltage levels (first or second read voltage level) based on the local condition of each memory cell's usage state. This localized approach improves bit reading accuracy for cells with varying storage states while maintaining overall read efficiency through automated selection.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9812194B1Decoding method, memory storage device and memory control circuit unit
Publication Date: 2017.11.07 PHISON ELECTRONICS
  • US9812194B1 patent drawing
  • US9812194B1 patent drawing
  • US9812194B1 patent drawing

AI summary

A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining usage state information of first memory cells; reading second memory cells by a first read voltage level to obtain at least one first bit and reading the second memory cells by a second read voltage level to obtain at least one second bit according to the usage state information, wherein the first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the second bit corresponds to a storage state of a second part of memory cell among the second memory cells, and the first read voltage level is different from the second read voltage level; and decoding third bits including the first bit and the second bit. Therefore, a decoding efficiency can be improved.