Memory Control Circuit Verify Error Aggregation
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Solution Overview
Problem
In existing memory systems, verification of data writing is performed on individual memories, which can lead to insufficient determination and a narrowed available range of memories when multiple memories are combined in a module.
Innovation Solution
A memory control circuit that divides write data and error correction codes into multiple memories, acquires verify error bit lengths from each memory, and determines successful writing based on the total bit length of verify errors falling within the error correction code's tolerance range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If verification is performed on individual memories separately, then the verification process is simple, but the available range of memories is narrowed and determination of successful writing is insufficient when multiple memories are combined
Solution Approach 1:
The patent merges the verification results from multiple memories by acquiring verify error bit lengths from each memory and evaluating them collectively. The write control unit combines individual verification outcomes to determine overall writing success, allowing the system to utilize more memories effectively while maintaining a manageable verification process through systematic aggregation of results.
2Reliability
If individual memory verification is performed, then the verification process is straightforward, but writing success determination is insufficient for memory modules combining multiple memories
Solution Approach 1:
The patent implements feedback by acquiring verify error bit lengths from each memory and feeding this information back to the write control unit. The write control unit uses this feedback to make informed decisions about writing success, comparing the total error bit length against the error correction code's capability to determine whether the writing operation succeeded or failed.
3Productivity
If verify errors in individual memories are treated as writing failures, then individual memory reliability is maintained, but the overall memory module utilization is reduced
Solution Approach 1:
The patent changes the evaluation parameter from binary (success/failure) at the individual memory level to a cumulative parameter (total verify error bit length) at the memory module level. This allows the system to tolerate verify errors in individual memories as long as the total error bit length remains within the error correction code's capability, thereby improving memory module utilization while maintaining reliability.
Data Source
AI summary
Provided is a memory access control unit that performs writing by dividing write data and an error correction code thereof into a plurality of memories, and acquires presence or absence of occurrence of a verify error in each of the plurality of memories related to the writing. In a case where the verify errors occur in at least any of the plurality of memories, an error bit length acquisition unit acquires bit lengths of the verify errors from the plurality of memories and a write control unit determines that the writing has succeeded if a total bit length of the verify errors falls within a range of a capability allocated to an error bit length tolerance of the error correction code, and determines that the writing has failed if the total bit length of the verify errors falls outside the range.