Memory Control Circuit for Multi-Type Memory Compatibility
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Solution Overview
Problem
Memory devices with multiple types of memory require different control schemes for read and write operations, leading to inefficiencies and incompatibilities between host error correction schemes and memory error correction codes.
Innovation Solution
A control circuit that generates internal commands based on access units of multiple memories, allowing for unified operation and error correction management, thereby eliminating the need for host-generated commands tailored to each memory type and enabling compatibility between different error correction schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different control schemes are used for each memory type, then each memory can operate according to its specific requirements, but the control circuit complexity increases and operation efficiency decreases
Solution Approach 1:
The control circuit is designed with a universal command generation mechanism that can handle multiple memory types (DDR3, DDR4, LPDDR3, LPDDR4) through a unified control scheme. The circuit generates appropriate internal commands based on memory type identification without requiring separate control paths for each memory type, thus achieving multi-functionality while maintaining simplicity.
Solution Approach 2:
The control circuit acts as an intermediary between the host and multiple memory types with different access units. It translates host commands into memory-specific internal commands using a unified control scheme, mediating the compatibility issues between different memory types and the host without exposing the complexity to either side.
2Measurement precision
If host generates commands tailored to each memory type, then precise control is achieved, but the host complexity increases and operation efficiency decreases
Solution Approach 1:
The control circuit implements self-service by automatically identifying the memory type and generating the appropriate internal commands without requiring the host to provide memory-specific control logic. The host simply issues generic commands, and the control circuit handles the memory-type-specific adaptations autonomously.
Solution Approach 2:
The control circuit serves as an intermediary that shields the host from memory type complexities. It receives generic commands from the host, identifies the target memory type, and generates the precise internal commands needed, thus maintaining command precision while simplifying host operation.
3Reliability
If error correction schemes are customized for each memory type, then error correction effectiveness is optimized, but the control complexity increases
Solution Approach 1:
The control circuit implements a universal error correction management mechanism that handles ECC operations for multiple memory types through a unified approach. It generates appropriate ECC commands based on memory type identification while using the same control logic path, achieving effective error correction across different memory types without multiplying the control complexity.
4Productivity
If access units are optimized for each memory type, then memory operation efficiency is maximized, but the incompatibility between host and memory increases
Solution Approach 1:
The control circuit acts as an intermediary that reconciles the different access units of various memory types with the host's unified interface. It translates host access patterns into memory-specific access units efficiently, maintaining optimal memory operation efficiency while ensuring host-memory compatibility through its mediating translation function.
Data Source
AI summary
A control circuit configured to associate a plurality of memory with an error correction scheme. The control circuit including an internal operation circuit configured to generate an internal command based on an access unit of the plurality of memory. The control circuit including a storage circuit configured to store information on the access unit of the plurality of memory.