Memory Control Circuit Parallel Data Transfer
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Solution Overview
Problem
Existing memory systems face challenges in optimizing data transfer rates between memory controllers and memory chips, particularly in scenarios where access requests are unpaired or vary in frequency.
Innovation Solution
The memory system employs a control circuit that generates access requests and determines their order for concurrent execution, allowing for parallel data transfers across multiple memory channels. This system includes a splitter/concatenator circuit that manages data concatenation and splitting to maintain a higher transfer rate through the host channel compared to individual memory channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed through multiple memory channels in parallel, then the overall data transfer rate is improved, but the complexity of managing unpaired access requests increases
Solution Approach 1:
The patent segments the data transfer management into two distinct components: a scheduler that generates and orders access requests, and a splitter/concatenator circuit that physically distributes and recombines data streams. This segmentation allows each component to focus on its specific function, reducing overall control complexity while maintaining high parallel transfer rates
Solution Approach 2:
The splitter/concatenator circuit acts as an intermediary between the host channel and multiple memory channels. It receives data from the host, splits it into appropriate channels, and recombines responses, thereby simplifying the control logic needed to manage unpaired access requests across multiple parallel channels
2Productivity
If the transfer rate of the host channel is increased to match the aggregate bandwidth of multiple memory channels, then data transfer efficiency is improved, but the difficulty of handling unpaired access requests worsens
Solution Approach 1:
The scheduler performs preliminary actions by pre-ordering access requests before they are sent to the memory channels. This advance organization of requests allows the system to maintain high host channel transfer rates without the complexity of dynamically managing unpaired requests during data transfer
Solution Approach 2:
The splitter/concatenator circuit serves as an intermediary that absorbs the complexity of handling unpaired access requests. It manages the distribution and recombination of data streams, allowing the host channel to operate at maximum transfer rate without direct involvement in the complex task of managing unpaired requests
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first circuit, multiple second circuits, and a first number of first channels connected to the first circuit. One or more second circuits are connected to each first channel. The control circuit is connected to the semiconductor memory device via a second channel. The control circuit generates multiple first access requests each for one of the second circuits. The control circuit determines order of execution of the first access requests to allow concurrent execution of a second number of first access requests designating two or more of the second circuits connected to different first channels. The control circuit executes in parallel the second number of data transfers responsive to the second number of first access requests via the second channel at a transfer rate the second number of times a transfer rate of one of the first number of first channels.