DRAM Memory Control Circuit Dynamic Read Write Prioritization

Solution Overview

Problem

Existing memory control circuits for DRAM experience performance degradation due to page misses and switching between read and write operations, as they do not effectively manage prioritization of commands to mitigate these issues.

Innovation Solution

A memory control circuit that includes a holding unit for access requests, a management unit for bank states, a determination unit to prioritize read or write commands based on access types and bank states, and an issuance unit to optimize command prioritization, thereby suppressing performance degradation caused by page misses and switching between read and write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read or write is set as a prioritized command and switched prioritized commands after having fetched all the prioritized commands from a command queue, then switching between read and write is suppressed, but performance degradation due to page misses cannot be suppressed

Engineering Contradiction:

ImproveDRAM performanceVSAvoidpage miss performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the command prioritization strategy adaptive rather than fixed. The determination unit dynamically selects between read-first and write-first prioritization based on real-time bank states and access request characteristics. This allows the system to respond to changing memory access patterns and suppress both switching penalties and page miss impacts appropriately.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of command prioritization strategy based on detected conditions. The determination unit modifies the prioritization approach (read-first vs. write-first) according to bank states, access types, and request characteristics. This parameter adaptation enables the system to optimize performance under different operational conditions, addressing both switching and page miss issues.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If prioritized commands are switched after fetching all prioritized commands from command queue, then command switching is reduced, but page misses cause performance degradation

Engineering Contradiction:

Improvecommand processing efficiencyVSAvoidpage miss time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having the determination unit analyze bank states and access requests before command execution. The management unit tracks bank states in advance, and the determination unit pre-determines the optimal prioritization strategy based on predicted access patterns. This preliminary analysis enables better command scheduling that accounts for potential page misses before they occur.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the management unit that continuously monitors bank states and feeds this information back to the determination unit. Based on this feedback, the determination unit adjusts command prioritization strategies in real-time. This closed-loop feedback mechanism allows the system to respond to actual memory access conditions and optimize both command processing efficiency and page miss handling.

Inventive Principle:

Principle #23Feedback

3Device complexity

If fixed read-first or write-first prioritization is used, then command queue processing is simplified, but performance cannot be optimized under varying bank states

Engineering Contradiction:

Improvecommand prioritization controlVSAvoidDRAM performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent changes the parameter of command prioritization strategy based on detected conditions. The determination unit modifies the prioritization approach (read-first vs. write-first) according to bank states, access types, and request characteristics. This parameter adaptation enables the system to optimize performance under different operational conditions, addressing both switching and page miss issues.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies dynamics by making the command prioritization strategy adaptive rather than fixed. The determination unit dynamically selects between read-first and write-first prioritization based on real-time bank states and access request characteristics. This allows the system to respond to changing memory access patterns and suppress both switching penalties and page miss impacts appropriately.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11923037B2Memory control circuit and method for controlling the same

Publication Date: 2024.03.05 CANON KK

AI summary

A memory control circuit is configured to access a memory including a plurality of banks. The memory control circuit comprises: a holding unit configured to hold an access request from an external circuit; a management unit configured to manage states of the plurality of banks; a determination unit configured to determine, based on an access type of an access request held in the holding unit and the states of the plurality of banks, which access type of command issuance that is read or write is to be prioritized; and an issuance unit configured to issue a command of an access request corresponding to the access type determined to be prioritized by the determination unit, among the access requests held in the holding unit.