Memory Control Circuit Priority Access Type Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random access memory (DRAM) performance degrades due to page misses and switching between read and write operations, as existing techniques fail to effectively execute access requests during priority access type switching, leading to performance bottlenecks.
Innovation Solution
A memory control circuit with a storage unit, status management unit, and access selection unit that classifies access requests, determines priority access types, and selectively executes access requests based on page miss times and switching times to prevent performance degradation by executing requests before and after priority access type switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If priority access type switching is performed by taking out all access requests of the priority access type from the command queue, then the switching between read and write operations can be completed, but page misses occur and access requests after switching cannot be executed, resulting in performance degradation
Solution Approach 1:
The patent applies preliminary action by executing access requests of the priority access type before switching before the priority access type switching is performed. This ensures that these requests are completed in advance, preventing page misses and ensuring they can be executed even when switching occurs. The control circuit identifies and executes these requests preliminarily, then performs the switching, and finally executes access requests of the priority access type after switching, thus resolving the contradiction between enabling switching and maintaining performance.
2Productivity
If access requests are executed during priority access type switching, then DRAM performance can be maintained, but complex control logic is required to manage timing and page miss prevention
Solution Approach 1:
The patent applies dynamics by making the control circuit's behavior adaptive based on the switching state. The control circuit dynamically adjusts its execution strategy: when priority access type switching is in progress, it executes access requests of the priority access type before switching; when switching is not in progress, it executes access requests of the priority access type. This dynamic adaptation allows the system to maintain performance while managing complexity through state-based control logic.
Data Source
AI summary
A memory control circuit includes an access storage unit configured to store access requests for a memory, a status management unit configured to, based on the access requests stored in the access storage unit, perform priority access type switching between two access types obtained by classifying the access requests, and an access selection unit configured to select and execute an access request stored in the storage unit. The access selection unit performs, if the priority access type switching is in progress and there is time for executing an access request of a priority access type before the priority access type switching, selecting the access request of the priority access type before the priority access type switching, and if the priority access type switching is not in progress, selecting an access request of the priority access type.