Memory Control Circuit Adaptive Delay Compensation SPI NOR Flash
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Solution Overview
Problem
Conventional memory control circuits for SPI NOR flash memory face data delays due to routing issues on circuit boards, leading to increased costs and complexity with the use of intermediary circuits to address asynchronous data problems.
Innovation Solution
A memory control circuit and method that utilize an interface control unit, serial control unit, and data control unit to manage clock signals and delay settings, allowing for adaptive compensation of signal delays without additional circuits by waiting for a predetermined time period that includes both read waiting and delay times, which are multiples of different clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an intermediary circuit is added to solve asynchronous data issues caused by routing delays, then data stability is improved, but circuit area and manufacturing costs increase
Solution Approach 1:
The patent extracts the delay compensation function from a separate intermediary circuit and integrates it into the memory control circuit. Specifically, the delay setting unit is incorporated within the memory control circuit to generate delayed clock signals, eliminating the need for external intermediary circuits while maintaining data stability.
Solution Approach 2:
The patent merges multiple functions into the memory control circuit: clock signal generation, delay adjustment, and data timing control are all integrated within this single circuit. This consolidation eliminates separate intermediary circuits, reducing circuit area while maintaining the ability to compensate for routing delays.
2Reliability
If an intermediary circuit is added to address routing delays, then data synchronization is improved, but manufacturing costs increase
Solution Approach 1:
The delay compensation functionality is extracted from external intermediary circuits and embedded within the memory control circuit itself. This integration eliminates additional components that would increase manufacturing complexity and cost, while still achieving proper data synchronization.
Solution Approach 2:
The memory control circuit is designed to perform multiple functions: it generates clock signals, adjusts delays through the delay setting unit, controls data timing, and manages communication with the SPI NOR flash memory. This multi-functionality eliminates the need for separate intermediary circuits, reducing manufacturing costs.
3Device complexity
If delay compensation is implemented using fixed timing, then circuit simplicity is maintained, but adaptability to different routing delays is reduced
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay setting unit can be configured with different delay values based on actual routing conditions. The memory control circuit adapts its timing by adjusting the delay of clock signals according to the specific routing delay characteristics, making the system flexible rather than fixed.
Solution Approach 2:
The patent changes the timing parameters of clock signals dynamically. The delay setting unit adjusts the delay parameter of clock signals based on measured or specified routing delays, allowing the system to adapt to different timing requirements without changing the physical circuit structure.
Data Source
AI summary
This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial peripheral interface (SPI) NOR flash memory; transmitting a read instruction to the SPI NOR flash memory; waiting for a read waiting time period, which is associated with a specification of the SPI NOR flash memory and a cycle of the first clock; waiting for a delay time period, which is associated with a delay setting value and a cycle of a second clock different from the first clock; receiving read data returned from the SPI NOR flash memory; and adjusting the delay time period according to whether the read data are correct or not. This invention improves the stability of read operation of the SPI NOR flash memory and has advantages of simple circuit and flexible adjustment.