Memory Control Circuit Constant Command Issuance Timing
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Solution Overview
Problem
DRAM noise interference affects the performance of electronic apparatuses, particularly in sensor modules where high detection accuracy is required, and existing methods like shifting refreshing operations or shield insertion are insufficient to prevent noise while maintaining data transfer bandwidth.
Innovation Solution
A memory control circuit and method that control the timing of command issuance to maintain a constant (tATP+tPTA) period, where tATP is the time from an ACT command to a PRE command and tPTA is the time from a PRE command to the next ACT command, thereby stabilizing the issuance cycles of these commands and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the timing of refreshing operations is shifted in multiple DRAM memory sections, then power supply noise is suppressed, but the complexity of memory control increases
Solution Approach 1:
The patent changes the timing parameters of ACT and PRE commands to achieve constant (tATP+tPTA), thereby controlling the issuance cycles of these commands. This parameter adjustment suppresses power supply noise while maintaining manageable control complexity through systematic timing management.
2Object-generated harmful factors
If shield insertion is used to reduce DRAM noise, then noise reduction is achieved, but device complexity and space requirements increase
Solution Approach 1:
The patent extracts the noise reduction function from physical shielding structures and implements it through software-based timing control of ACT and PRE commands. This eliminates the need for additional shield components while achieving the same noise suppression effect.
3Object-generated harmful factors
If command issuance timing is controlled to reduce noise, then noise generated during memory access is reduced, but data transfer bandwidth may be impaired
Solution Approach 1:
The patent adjusts the timing parameters tATP and tPTA of ACT and PRE commands to achieve constant (tATP+tPTA). This parameter optimization reduces memory access noise while maintaining data transfer bandwidth by ensuring efficient utilization of memory banks through proper timing coordination.
Data Source
AI summary
A memory control circuit of the disclosure includes a memory control unit that controls a timing of command issuance to cause (tATP+tPTA) to be constant, where, in a memory having a plurality of banks, tATP is a period from issuance of a first ACT command to issuance of a PRE command that is directed a bank same as or different from a bank to which the first ACT command is issued, and tPTA is a period from the issuance of the PRE command to issuance of a second ACT command that is directed to a bank same as or different from the bank to which the PRE command is issued.