Memory Control Circuit Unit Parallel Write and Data Collection

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Solution Overview

Problem

In multi-channel memory storage devices, the performance is deteriorated due to busy channels being unable to collect valid data in real-time, leading to inefficiencies during data merge processes, as other channels are unable to write data until the busy channel completes its operations.

Innovation Solution

A memory control method that performs a first write operation and a limited data collection operation, allowing a second write operation to occur concurrently, where the second data is written to a different physical group, ensuring that data collection from the first group is completed only after the first write operation is finished, thereby releasing spare physical units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a channel performs a write operation to complete data merge, then data integrity is ensured, but the channel is occupied and cannot collect valid data from other physical groups simultaneously, leading to reduced system throughput

Engineering Contradiction:
Improvedata integrityVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the data collection task into multiple segments corresponding to different physical groups. While one channel (e.g., first channel) is performing a write operation on the first physical group, other channels (e.g., second, third, fourth channels) simultaneously collect valid data from other physical groups (second, third, fourth physical groups). This segmentation allows parallel execution of data collection across multiple channels without interfering with the ongoing write operation, thereby maintaining data integrity while improving system throughput.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a channel waits for another channel to complete write operation before collecting valid data, then data consistency is maintained, but waiting time increases and reduces operational efficiency

Engineering Contradiction:
Improvedata consistencyVSAvoidwaiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by having channels collect valid data in advance from physical groups that are not currently being written to. For example, while the first channel writes data to the first physical group, the second channel proactively collects valid data from the second physical group beforehand. This preliminary data collection eliminates waiting time because the data is already prepared and available when needed, maintaining data consistency while significantly reducing idle waiting periods.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If multiple channels perform data collection simultaneously, then system utilization is improved, but the complexity of managing concurrent operations increases

Engineering Contradiction:
Improvesystem utilizationVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent manages concurrent operations by segmenting the memory space into distinct physical groups (first, second, third, fourth physical groups) and assigning specific channels to specific physical groups. This segmentation creates a clear mapping between channels and physical groups, simplifying the control logic for managing concurrent operations. Each channel knows which physical group to access, reducing the complexity of coordinating multiple simultaneous data collection operations while maintaining high system utilization.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11048433B2Memory control method with limited data collection operations, memory storage device and memory control circuit unit
Publication Date: 2021.06.29 PHISON ELECTRONICS
  • US11048433B2 patent drawing
  • US11048433B2 patent drawing
  • US11048433B2 patent drawing

AI summary

A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The memory control method includes: performing a first write operation to write first data to a first physical unit in a first physical group through a first channel; performing a limited data collection operation to collect second data, wherein the limited data collection operation limits that the second data does not include data to be collected from the first physical group after the first write operation is completed; and performing a second write operation during a period of performing the first write operation, so as to write the second data to a second physical unit in the second physical group through a second channel. In addition, the limited data collection operation and the second write operation are configured to release at least one spare physical unit.