Memory Control Circuit for Variable Width Data Storage
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Solution Overview
Problem
Existing memory control systems face inefficiencies in data storage and processing when handling data with different widths, leading to either wasted memory space or increased processing loads due to the need for packing and unpacking data.
Innovation Solution
A memory control circuit that manages multiple k-bit memories to store and retrieve data of varying widths by using a start-position specification address to determine the storage and retrieval of divided data across multiple memory units, eliminating the need for packing and unpacking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored at one address per piece, then data access is simple, but memory usage efficiency deteriorates due to unused data areas
Solution Approach 1:
The patent merges multiple k-bit memory units into a unified memory system that can handle D-bit data (where D is an integral multiple of k). By combining m=k×(D/k) memory units and using a unified addressing mechanism, the system stores D-bit data across multiple memory units simultaneously, eliminating unused data areas and achieving full memory utilization without compromising access simplicity.
2Quantity of substance
If multiple data with different widths are packed into memory, then memory usage efficiency improves, but processing load increases due to packing and unpacking processes
Solution Approach 1:
The patent segments D-bit data into multiple k-bit units that can be stored across m=k×(D/k) memory units. Each memory unit stores a portion of the data, and the segmentation is managed through address decomposition (separating start-position specification address from the remaining address bits) and data width specification, eliminating the need for complex packing and unpacking operations.
Solution Approach 2:
The patent implements dynamic memory allocation where the number of active memory units and their addressing is automatically adjusted based on the data width parameter. The system dynamically determines which memory units to use and how to address them based on the actual data width, allowing flexible handling of different data widths without fixed packing structures or additional processing overhead.
3Adaptability or versatility
If data width is less than L bits, then storage flexibility improves, but unused data areas are generated
Solution Approach 1:
The patent changes the addressing parameters and memory activation parameters based on the data width. By adjusting the number of active memory units and their addressing scheme according to the actual data width (which is an integral multiple of k bits), the system maintains full memory utilization while accommodating different data widths. The start-position specification address and data width specification work together to dynamically configure memory usage.
Data Source
AI summary
A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circuit that determines a memory (nth memory) storing a first k bits of the data among the m memories, based on a start-position specification address which is a predetermined j bits of an A-bit address indicating a storage destination of the data, and inputs to the nth to mth memories a first specification address for specifying a storage destination of the data, the first specification address being an A-j bits of the A-bit address, which is the A-bit address without the predetermined j bits thereof, and inputs to the first to (n−1)th memories a second specification address obtained by adding one to the first specification address; a data input circuit that inputs a plurality of pieces of divided data obtained by dividing the data into k-bit data to the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address; a data output circuit that reads the plurality of pieces of divided data from the memories respectively, in the order of the nth to mth memories and the first to (n−1)th memories, the number of the memories corresponding to the data width of the data, and outputs the read plurality of pieces of divided data as the data, based on the start-position specification address; and a memory selecting circuit that makes the D/k memories readable/writable, in the order of the nth to mth memories and the first to (n−1)th memories, based on the start-position specification address and the data width of the data.