Memory Control Circuitry Erratic Programming Detection
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Solution Overview
Problem
Existing memory device programming techniques fail to detect erratic programming during the programming operation, leading to over-programming and subsequent failures, which are only identified after the operation is completed, resulting in increased programming time and potential data loss.
Innovation Solution
The implementation of a method that uses incremental step pulse programming with verify pulses to simultaneously check the upper and lower tails of memory cells' threshold voltages in each programming loop, allowing for real-time detection of erratic programming and prevention of further programming if errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming operation completes without real-time verification, then programming speed is maintained, but erratic programming is not detected leading to over-programming and failures
Solution Approach 1:
The patent applies preliminary action by performing verification of memory cell thresholds during the programming operation itself, rather than waiting until completion. The verify pulse is applied in each programming loop to check whether memory cells have reached their target threshold voltage before the programming operation is complete, allowing early detection of erratic programming and prevention of over-programming.
Solution Approach 2:
The patent implements feedback by using the verification result from each programming loop to control whether subsequent programming continues. The verify pulse measures the threshold voltage of memory cells, and this measurement feedback determines whether the programming operation should proceed to the next loop or be terminated, preventing waste of time on already-programmed or erratically programmed cells.
2Reliability
If verify pulse is applied in each programming loop, then erratic programming is detected in real-time, but programming operation becomes more complex
Solution Approach 1:
The patent merges the verification function with the existing programming operation by integrating the verify pulse application into each programming loop. Rather than adding a separate verification phase, the verification is combined with the programming loops, allowing erratic programming detection without significantly increasing overall system complexity.
Solution Approach 2:
The verify pulse serves multiple functions: it verifies whether memory cells have reached the target threshold voltage, detects erratic programming conditions, and controls the continuation of programming operations. This multi-functionality reduces the need for additional dedicated verification circuits or operations, thereby limiting the increase in device complexity.
3Productivity
If programming continues without detection, then programming speed is maintained, but over-programming occurs causing data loss
Solution Approach 1:
The verification result feeds back to control the programming operation, preventing over-programming. When the verify pulse indicates that memory cells have reached the target threshold voltage or when erratic programming is detected, the feedback mechanism terminates further programming, thereby preventing data loss while maintaining efficient programming speed through real-time monitoring.
Solution Approach 2:
The patent converts the potentially harmful effect of continuous programming (which could lead to over-programming and data loss) into a beneficial outcome by using the verification process to detect and prevent erratic programming. The verify pulse, which adds some operational complexity, ultimately protects against data loss and ensures reliable programming completion.
Data Source
AI summary
The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N−1. The data state N−1 has a lower voltage threshold than the data state N.


