Memory Control Circuitry for DRAM and MRAM Access Optimization
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Solution Overview
Problem
Current memory systems in portable information terminals face inefficiencies due to the high access time for non-successive address areas in DRAM and lower access speed for successive address areas in MRAM, necessitating a solution to optimize memory access and writing operations.
Innovation Solution
A memory control circuitry with a write destination selector, access information register, and page switching times counter dynamically allocates memory access between volatile DRAM and non-volatile MRAM based on page switching frequencies, optimizing write operations by selecting the most suitable memory type for each address area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for memory access, then access speed to successive address areas is improved, but access time to non-successive address areas increases
Solution Approach 1:
The system dynamically switches between DRAM and MRAM based on access patterns. The write destination selector changes the memory destination according to whether successive or non-successive address areas are being accessed, making the memory system adaptive rather than static.
Solution Approach 2:
The system changes the parameter of memory destination (DRAM or MRAM) based on the access pattern. When successive address areas are accessed, DRAM is selected; when non-successive address areas are accessed, MRAM is selected. This parameter change optimizes performance for different access scenarios.
2Speed
If MRAM is used for memory access, then access speed to non-successive address areas is improved, but access speed to successive address areas decreases
Solution Approach 1:
The system dynamically selects between MRAM and DRAM based on the access pattern. The write destination selector monitors whether successive or non-successive address areas are being accessed and switches the memory destination accordingly, optimizing for each scenario.
Solution Approach 2:
The memory destination parameter is changed based on access patterns. For non-successive address areas, MRAM is selected to maximize access speed; for successive address areas, DRAM is selected to maintain high productivity.
3Device complexity
If a single memory type is used, then system complexity is reduced, but memory system performance is limited
Solution Approach 1:
The memory system is segmented into two parts: DRAM for successive address areas and MRAM for non-successive address areas. The write destination selector segments the memory access paths based on access patterns, allowing each memory type to optimize its performance for its designated scenario.
Solution Approach 2:
The memory system achieves multi-functionality by combining DRAM and MRAM, each serving different access patterns. The write destination selector enables the system to universally handle both successive and non-successive address area accesses with optimal performance for each case.
Data Source
AI summary
A memory control circuitry has a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor, a write controller to write data in the write destination selected by the write destination selector, and an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other. When there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register.