Memory Control Circuit Dynamic Clock Selection
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Solution Overview
Problem
Existing memory device control circuits are limited in varying operation timing due to their reliance on constant clock signals, which restricts the flexibility in performing program, read, or erasure operations.
Innovation Solution
A control circuit with a command interface, clock selection signal output circuit, and clock generating circuit that outputs different clock periods based on sub-operation importance, allowing for flexible adjustment of operation timing by using multiple clocks with varying periods for different sub-operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a constant clock signal is used for controlling operations, then the control circuit structure is simple, but the operation timing flexibility is limited
Solution Approach 1:
The control circuit segments the operation control into multiple sub-operations, each with its own clock signal. The clock generation unit generates first and second clock signals with different periods, and the control unit selectively applies them to different sub-operations based on importance, thereby achieving timing flexibility without requiring complete redesign of the control structure.
Solution Approach 2:
The patent introduces dynamic clock period selection by generating multiple clock signals with different periods and selectively applying them based on operation requirements. The control unit dynamically switches between clock signals depending on which sub-operation is being executed, making the system adaptable while maintaining a relatively simple overall structure.
2Loss of time
If shorter clock periods are used for all sub-operations, then the overall operation time is reduced, but the reliability of critical operations may be compromised
Solution Approach 1:
The patent applies different clock periods to different sub-operations based on their importance. Critical sub-operations use the first clock signal with a longer period to ensure reliability, while non-critical sub-operations use the second clock signal with a shorter period to reduce overall operation time. This localized differentiation resolves the contradiction between speed and reliability.
Solution Approach 2:
The control circuit changes the clock period parameter dynamically based on the type of sub-operation being executed. By adjusting the clock period according to operation criticality, the system achieves both reduced overall operation time and maintained reliability for essential functions.
3Reliability
If longer clock periods are used for all sub-operations, then the reliability of critical operations is maintained, but the overall operation time increases
Solution Approach 1:
The patent applies longer clock periods only to critical sub-operations that require high reliability, while using shorter clock periods for non-critical operations. This selective application maintains reliability where needed while improving overall operation efficiency by not unnecessarily slowing down less important tasks.
Solution Approach 2:
The system dynamically changes the clock period parameter based on operation requirements, using longer periods for reliability-critical operations and shorter periods for efficiency-critical operations, thereby optimizing the balance between reliability and productivity.
4Adaptability or versatility
If multiple clocks with different periods are used, then the operation timing flexibility is improved, but the device complexity increases
Solution Approach 1:
The control circuit is segmented into distinct functional units: a clock generation unit that produces multiple clock signals, and a control unit that selectively applies them. This segmentation allows the system to achieve timing flexibility through modular design rather than through complex interwoven control logic.
Solution Approach 2:
The control unit serves multiple functions: it decodes commands, determines operation types, selects appropriate clock signals, and coordinates peripheral circuits. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity despite the use of multiple clocks.
Data Source
AI summary
In an embodiment, a control circuit may include a command interface, a clock selection signal output circuit, and a clock generating circuit. The command interface may output a selection enable signal in response to a command. The clock selection signal output circuit may output, in response to the selection enable signal, a clock selection signal according to various sub-operations performed in a selected operation. The clock generating circuit may generate main clocks having different periods according the clock selection signal.