Memory Control Circuit Unit Dynamic Data Rate Adjustment
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Solution Overview
Problem
The data writing speed of memory storage devices becomes unstable when performing a data merge operation, as the reduction in spare physical blocks necessitates simultaneous data writing and garbage collection, disrupting the steady data transfer with the host system.
Innovation Solution
A data storage method that adjusts the data receiving amount per unit time based on the storage state of the rewritable non-volatile memory module, storing to-be-written data in a buffer memory during the data merge operation and then transferring it to the memory module, maintaining a steady data writing speed by dynamically controlling the data transmission parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory device performs a data merge operation to release spare physical blocks, then the number of spare physical blocks increases, but the data writing speed becomes unsteady
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the host system and the non-volatile memory module. During data merge operations, incoming data from the host is temporarily stored in the buffer memory, allowing the memory device to perform garbage collection without directly impacting the data writing speed perceived by the host system. This mediator absorbs the performance degradation caused by the data merge operation.
Solution Approach 2:
The patent performs preliminary actions by pre-allocating buffer memory space and proactively managing data transfer timing. Before the data merge operation completes, the system prepares the buffer to receive incoming data, ensuring that data flow can continue uninterrupted. The control circuit anticipates the need for spare blocks and manages the data merge operation in advance, minimizing its impact on ongoing write operations.
2Quantity of substance
If data is continuously written to the memory device while spare physical blocks are depleted, then data storage capacity is utilized, but the data merge operation disrupts steady data transfer
Solution Approach 1:
The buffer memory acts as a stabilizing intermediary that decouples the host system's continuous data writing from the memory device's periodic data merge operations. By buffering incoming data, the system maintains stable data transfer characteristics from the host perspective, while internally handling the disruptive merge operations needed to maintain storage capacity.
Solution Approach 2:
The patent implements dynamic control of data transfer parameters based on the operational state of the memory device. The control circuit adjusts data receiving rates and buffer management strategies dynamically - increasing buffering during merge operations and optimizing data flow when merges are complete. This dynamic adaptation maintains overall system stability while accommodating varying operational demands.
Data Source
AI summary
A data storage method is provided according to an exemplary embodiment of the disclosure. The method is configured for a rewritable non-volatile memory module. The method includes: performing a data merge operation; adjusting a data receiving amount per unit time for receiving to-be-written data from a host system according to a data storage state of the rewritable non-volatile memory module; storing the received to-be-written data into a buffer memory during the data merge operation being performed; and storing the data stored in the buffer memory into the rewritable non-volatile memory module.