Memory Control Circuit Dynamic Sorting for Decoding Efficiency

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Solution Overview

Problem

The efficiency of data decoding in rewritable non-volatile memory modules is hindered by changes in threshold voltage distribution, leading to decreased data decoding efficiency due to sequential querying of management forms in a preset order.

Innovation Solution

A memory management method that adjusts sorting information based on error bit information to optimize the usage order of candidate management information for read voltage levels, allowing for improved data decoding correctness and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple management forms are stored and sequentially queried according to a preset order to determine read voltage levels, then data reading can be performed with multiple voltage level options, but data decoding efficiency decreases due to changes in threshold voltage distribution of memory cells

Engineering Contradiction:
Improveread voltage level selectionVSAvoiddata decoding efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies dynamics by transitioning from a static preset ordering of management forms to a dynamic ordering mechanism. The controller adjusts the usage order of management forms based on real-time error bit information from decoding operations, allowing the system to adapt to changing threshold voltage distributions. This dynamic reordering enables the system to maintain high decoding efficiency while preserving the ability to select from multiple read voltage levels.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by using error bit information from the decoding process to adjust the ordering of management forms. The controller monitors decoding performance and feeds this information back to reorder the management forms, creating a closed-loop system that continuously optimizes read voltage level selection based on actual memory cell conditions, thereby resolving the efficiency problem while maintaining adaptability.

Inventive Principle:
Principle #23Feedback

2Reliability

If sequential querying of management forms is used to handle threshold voltage distribution changes, then all possible read voltage levels can be tried, but the decoding process takes longer time

Engineering Contradiction:
Improvedata decoding correctnessVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-ordering management forms based on their expected effectiveness for current threshold voltage conditions. Instead of sequentially trying all management forms when decoding fails, the controller uses error bit information to identify and prioritize the most suitable management form in advance, significantly reducing the time required to achieve successful decoding while maintaining high correctness.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If a fixed preset order of management forms is used, then the system structure is simple, but it cannot adapt to changes in threshold voltage distribution

Engineering Contradiction:
Improvemanagement form structureVSAvoidadaptation to threshold voltage changes
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent resolves this contradiction by making the management form ordering dynamic rather than fixed. The controller maintains a simple data structure for storing management forms but dynamically adjusts their usage order based on error bit feedback. This approach preserves structural simplicity while enabling full adaptability to threshold voltage distribution changes through runtime reordering.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11809706B2Memory management method, memory storage device, and memory control circuit unit
Publication Date: 2023.11.07 PHISON ELECTRONICS
  • US11809706B2 patent drawing
  • US11809706B2 patent drawing
  • US11809706B2 patent drawing

AI summary

A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.