Memory Control Circuit Unit ECC Allocation for Storage Efficiency
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Solution Overview
Problem
Conventional data storage methods in non-volatile memory modules do not optimally utilize storage space for error correction codes (ECC) across physical programming units with varying reliability levels, leading to inefficient error correction and storage space utilization.
Innovation Solution
A data access method that generates different error correction codes for physical programming units based on their reliability levels, writing a first ECC and partial ECCs to the redundant bit areas of units with higher reliability, optimizing decoding capability and storage space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed size redundant bit area is used to store ECC in all physical programming units, then the storage space is uniformly allocated, but the decoding capability is insufficient for low reliability units and wasteful for high reliability units
Solution Approach 1:
The patent applies local quality by allocating different amounts of ECC storage space to different physical programming units based on their reliability characteristics. Low reliability units (upper PPUs) receive larger ECC allocations while high reliability units (lower PPUs) receive smaller allocations, optimizing both data integrity and storage space utilization for each specific unit type.
Solution Approach 2:
The patent changes the parameter of ECC storage space allocation from a fixed value to a variable value that depends on the reliability level of the physical programming unit. This parameter change allows the system to adapt the redundant bit area size to match the actual error correction needs of each unit type.
2Reliability
If more ECC bits are allocated to low reliability physical programming units, then the error correction capability is improved, but the storage space consumption increases
Solution Approach 1:
The patent implements local quality by providing enhanced ECC protection only to the specific physical programming units that require it (upper PPUs with lower reliability), while using minimal ECC for units with high reliability (lower PPUs). This localized approach improves error correction capability where needed without unnecessarily increasing storage space consumption across all units.
Solution Approach 2:
The patent applies partial action by allocating ECC resources selectively rather than uniformly. Instead of providing maximum ECC protection to all units, it provides partial ECC to high reliability units and excessive (full) ECC to low reliability units, optimizing the balance between protection and space usage.
3Quantity of substance
If the number of ECC bits varies across physical programming units, then the storage space is optimized, but the system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the physical programming units into distinct groups (upper and lower PPUs) with different reliability characteristics and corresponding different ECC allocation strategies. This segmentation simplifies the management complexity by creating clear categories rather than requiring individualized handling of each unit.
Solution Approach 2:
The patent implements universality by creating a multi-functional ECC management system that can handle both high and low reliability units with a single unified approach. The system automatically selects the appropriate ECC allocation strategy based on the unit type, providing universal functionality across different reliability scenarios without requiring separate management systems.
Data Source
AI summary
A data access method, a memory control circuit unit and a memory storage device are provided. The method includes generating a first error correction code corresponding to received first data according to a first error correction encoding operation; and generating a second error correction code corresponding to received second data according to a second error correction encoding operation, wherein the second error correction code includes a first and a second partial error correction code. The method further includes writing the first data, the first error correction code and the second partial error correction code to a data bit area and a redundant bit area of a first physical programming unit respectively; and writing the second data and the first partial error correction code to the data bit area and the redundant bit area of a second physical programming unit respectively.