Memory Control Apparatus for Pipelined Memory ECC Redundancy
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Solution Overview
Problem
Existing memory access methods, particularly in pipelined memories, suffer from redundant data reading and increased power consumption due to the need to read error correcting codes (ECC) from successive addresses, leading to inefficiencies and performance losses.
Innovation Solution
A memory control apparatus that utilizes a cache area to store read data and determines whether requested data is cached, allowing for partial read commands to be issued after a delay, thereby avoiding redundant reads and optimizing memory access in pipelined systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is read from successive addresses in pipelined memory using vertical ECC, then error correction is achieved, but redundant reading occurs causing performance loss and increased power consumption
Solution Approach 1:
The patent applies preliminary action by determining in advance whether the second data to be read is actually needed by checking if it will be used for error correction of subsequently read data. If not needed, the read operation is skipped entirely, avoiding redundant memory accesses before they occur.
Solution Approach 2:
The patent implements partial action by selectively performing only the necessary read operations. Instead of always reading both the first data and second data from successive addresses, the system performs a partial read (only the first data) when the second data is not required, thereby avoiding excessive memory access actions.
2Reliability
If data is read from successive addresses in pipelined memory using vertical ECC, then error correction is achieved, but electrical power consumption increases
Solution Approach 1:
The patent applies preliminary action by determining in advance whether the second data to be read is actually needed by checking if it will be used for error correction of subsequently read data. If not needed, the read operation is skipped entirely, avoiding redundant memory accesses before they occur.
Solution Approach 2:
The patent implements partial action by selectively performing only the necessary read operations. Instead of always reading both the first data and second data from successive addresses, the system performs a partial read (only the first data) when the second data is not required, thereby avoiding excessive memory access actions.
3Reliability
If the second data is read twice from memory, then error correction can be performed, but memory access overhead increases
Solution Approach 1:
The patent applies preliminary action by determining in advance whether the second data to be read is actually needed by checking if it will be used for error correction of subsequently read data. If not needed, the read operation is skipped entirely, avoiding redundant memory accesses before they occur.
Solution Approach 2:
The patent applies self-service by having the memory control apparatus autonomously determine whether redundant reads are necessary based on the read request patterns and memory address sequences. The system serves itself by making intelligent decisions about when to skip reads, eliminating the need for external control mechanisms.
Data Source
AI summary
An internal buffer caches data from a memory. A memory address conversion unit receives as input a read request from a request source. A hit determination unit determines whether or not data of any one of two or more read out candidate addresses in which payload data requested by the read request and corresponding are stored has been cached or is going to be cached in the internal buffer. When data of any one of the addresses has been cached or is going to be cached in the internal buffer, a command issue interval control unit outputs to the memory a partial read command to instruct to read data from an address other than the address of the data that has been cached or is going to be cached in the internal buffer out of the read out candidate addresses, after a predetermined delay time has elapsed.