Memory Control Circuit Unit Error Bit Analysis

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Solution Overview

Problem

Existing methods cannot accurately determine the state of a rewritable non-volatile memory module, leading to potential data loss as they rely solely on the maximum error bit number, failing to account for the condition of other physical programming units within a physical erasing unit.

Innovation Solution

A memory management method that records and analyzes the error bit numbers of upper and lower physical programming units within each physical erasing unit, using parameters like mean, standard deviation, and median to determine if a physical erasing unit is deteriorated, thereby initiating data transfer operations to prevent data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If only the maximum error bit number is used to determine memory module deterioration, then the determination process is simple, but the accuracy of determining memory state is insufficient leading to potential data loss

Engineering Contradiction:
Improveaccuracy of memory state determinationVSAvoidcomplexity of error analysis
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the error bit number analysis into multiple dimensions: upper physical programming unit error bit numbers, lower physical programming unit error bit numbers, and their statistical distributions. This segmentation allows comprehensive assessment of memory deterioration by examining different parts of the error distribution separately, thereby improving measurement precision without overwhelming complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the single parameter approach (maximum error bit number) into multiple parameters including mean, standard deviation, and median of error bit numbers. This parameter transformation enables more accurate determination of memory module deterioration by capturing the distribution characteristics of errors across different physical programming units

Inventive Principle:
Principle #35Parameter changes

2Reliability

If comprehensive error bit distribution analysis is performed on all physical programming units, then the accuracy of memory state determination is improved, but the operation complexity increases

Engineering Contradiction:
Improvereliability of data protectionVSAvoidease of memory management operation
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent performs preliminary analysis by calculating statistical parameters (mean, standard deviation, median) of error bit numbers before making deterioration determination. This preliminary action prepares the data in advance, making the final judgment process simpler and more reliable, thereby improving ease of operation while maintaining high reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the determined state of the first physical erasing unit feeds back into the memory management system, triggering appropriate data transfer operations. This feedback loop ensures reliable data protection by automatically responding to detected deterioration conditions

Inventive Principle:
Principle #23Feedback

3Reliability

If data transfer operation is performed only when maximum error bit exceeds threshold, then the operation is simple, but data loss prevention is insufficient

Engineering Contradiction:
Improvedata loss prevention capabilityVSAvoiddata writing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary determination of physical erasing unit deterioration using statistical analysis before data loss occurs. By identifying deteriorated units in advance through comprehensive error distribution analysis, the system can proactively transfer data, thereby improving data loss prevention capability without causing excessive data transfer operations that would reduce productivity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10685735B1Memory management method, memory storage device and memory control circuit unit
Publication Date: 2020.06.16 PHISON ELECTRONICS
  • US10685735B1 patent drawing
  • US10685735B1 patent drawing
  • US10685735B1 patent drawing

AI summary

The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.