Memory Control Circuit Error Thresholding for MRAM Cache Reliability
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Solution Overview
Problem
MRAMs used as cache memory are unreliable in writing and data retention, requiring an ECC error correction mechanism that incurs significant area and latency overhead, and may terminate as a fatal error due to uncorrectable errors, leading to system crashes.
Innovation Solution
A memory control circuit with an error detector, error correction circuitry, and access controller that determines the number of error bits and controls access to a secondary memory based on a threshold value, allowing for write-through or write-back operations to maintain data integrity and reduce system crashes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC error correction mechanism is incorporated to correct errors in MRAM cache memory, then data reliability is improved, but area overhead and latency overhead increase significantly
Solution Approach 1:
The patent applies partial error correction by determining the number of error bits and comparing it with a threshold value. When the error bit count is within the threshold, only partial correction is performed; when exceeding the threshold, the system switches to accessing higher-level memory. This selective approach reduces the area and latency overhead compared to full ECC correction while maintaining acceptable data reliability for cases with fewer errors.
2Use of energy by moving object
If MRAMs are used as cache memory to replace SRAMs, then power consumption is reduced, but writing reliability and data retention reliability deteriorate
Solution Approach 1:
The patent introduces an intermediary error detection and management system between the MRAM cache and the higher-level memory. This intermediary monitors error bits, determines their count, and decides whether to correct errors locally or access higher-level memory, thereby bridging the reliability gap between power-efficient MRAM and reliable traditional memory systems.
Solution Approach 2:
The system dynamically changes operational parameters by adjusting the threshold value for error bits based on system requirements and MRAM characteristics. This allows flexible adaptation of the error tolerance level, enabling the system to optimize between power consumption and data reliability by changing the decision parameter for error handling.
3Reliability
If uncorrectable error occurs in ECC process, then data integrity is maintained, but system crashes occur due to fatal error termination
Solution Approach 1:
The patent performs preliminary error detection and counting before attempting full correction. By determining the number of error bits in advance and comparing with the threshold, the system proactively identifies cases that would lead to uncorrectable errors and handles them by accessing higher-level memory, preventing fatal crashes before they occur.
Solution Approach 2:
The system prepares backup error handling strategies in advance by having higher-level memory accessible as a fallback. When error bits exceed the correctable threshold, the system smoothly transitions to accessing higher-level memory, cushioning against the impact of uncorrectable errors and maintaining system continuity without crashes.
Data Source
AI summary
A memory control circuit has an error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that an error is contained in data read for verification of data written to the first memory or in data read from the first memory, and an access controller to control access to a second memory having an access priority lower than the first memory when it is determined that the error-bit number is larger than the threshold value, and to control access to the first memory without accessing the second memory when it is determined that the error-bit number is equal to or less than the threshold value.