Memory Control Logic for Internal Command Generation and MAC Execution
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Solution Overview
Problem
Existing memory systems face issues with data transfer speed and power consumption due to the overload of the I/O bus from multiple commands and data transfers between an external controller and the memory device, leading to decreased efficiency.
Innovation Solution
Implementing control logic within the memory device to generate internal commands and addresses, reducing the need for external data transfer by generating commands internally and incrementing addresses for subsequent commands, thereby minimizing data transfer over the I/O bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple commands are sent from external controller to memory device through I/O bus, then memory operations can be executed, but the I/O bus becomes overloaded and data transfer speed decreases
Solution Approach 1:
The patent extracts the command generation function from the external controller and relocates it to the memory device's control logic. This allows the memory device to generate internal commands autonomously after receiving a single external command, reducing the number of commands that must be transmitted through the I/O bus and thereby preventing bus overload while maintaining operational productivity.
Solution Approach 2:
The memory device is enabled to serve itself by generating internal commands autonomously through its control logic. Once an external command is received, the control logic automatically generates the necessary internal commands without requiring continuous external intervention, making the system self-sufficient and reducing I/O bus dependency.
2Productivity
If multiple commands and data are transferred between external controller and memory device, then memory operations are completed, but power consumption increases
Solution Approach 1:
The command generation function is extracted from the external controller and implemented within the memory device's control logic. This architectural change reduces the volume of data that must be transmitted through the power-consuming I/O interface, thereby lowering overall power consumption while maintaining full memory operation functionality.
Solution Approach 2:
By enabling the memory device to generate its own internal commands autonomously, the system eliminates the need for continuous power-intensive data transmission between the external controller and memory device, achieving energy efficiency through self-sufficient operation.
3Speed
If control logic generates internal commands within memory device, then data transfer over I/O bus is minimized, but device complexity increases
Solution Approach 1:
The control logic within the memory device is designed to perform multiple functions: receiving external commands, generating internal commands autonomously, and managing memory operations. This multi-functional approach consolidates what would otherwise require separate components, achieving the desired speed improvement without proportionally increasing overall device complexity.
4Productivity
If external controller sends multiple commands through I/O bus, then memory operations are executed, but I/O bus overload occurs
Solution Approach 1:
The command generation function is extracted from the external controller and relocated to the memory device's control logic. This extraction reduces the volume of data that must be transmitted through the I/O bus from multiple commands to a single external command, preventing bus overload while maintaining full memory operation execution capability.
Solution Approach 2:
The memory device generates its own internal commands autonomously through control logic, making the system self-sufficient. This self-service capability dramatically reduces the quantity of data that must be transferred through the I/O bus, eliminating the root cause of bus overload while preserving complete memory operation functionality.
Data Source
AI summary
An apparatus comprising an array of memory cells, a register coupled to the array of memory cells, and control logic coupled to the register and the array of memory cells. The control logic is configured to issue an internal command in response to a memory controller receiving an external command, generate an address corresponding to the internal command, provide the internal command to a row decoder and a column decoder, and instruct a processing unit (PU) to perform multiply-accumulate (MAC) operations on received data.