Memory Control Circuit Dynamic Interruption Transmission

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory storage devices face inefficiencies due to frequent switching between host command processing and checking procedures, leading to increased system loading and reduced data processing performance, especially when command queue depth is shallow or response timeouts occur.

Innovation Solution

A memory management method that dynamically determines the transmission mode of interruption messages based on command processing information, allowing for optimal transmission frequency regardless of queue depth, thereby avoiding response timeouts and reducing unnecessary procedure switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the memory storage device transmits interruption messages after each operation command completion, then the host system can respond quickly to commands, but the host system must frequently switch between command processing and checking procedures, increasing system loading

Engineering Contradiction:
Improvecommand response speedVSAvoidsystem processing efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies dynamics by making the interruption message transmission mode adjustable and adaptive. The system dynamically switches between first transmission mode (transmitting after each command completion) and second transmission mode (transmitting after multiple commands or timeout) based on command queue depth and system state, optimizing both response speed and processing efficiency under different conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the transmission parameter (interruption message frequency/timing) based on command queue depth and system state. When queue depth is shallow, it uses first transmission mode for quick response; when queue depth is deep, it switches to second transmission mode to reduce switching frequency, thereby adapting the system behavior to current load conditions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the memory storage device reduces interruption message transmission frequency to lower system loading, then the host system processing efficiency improves, but the command queue depth may become shallow and reaction efficiency decreases

Engineering Contradiction:
Improvesystem processing efficiencyVSAvoidcommand reaction efficiency
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent implements feedback by monitoring command queue depth and using it to adjust the interruption message transmission mode. The system continuously checks the queue depth and switches between transmission modes accordingly, ensuring that the transmission frequency adapts to the current system state and maintains optimal reaction efficiency

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts the interruption message transmission strategy based on real-time queue depth monitoring. When queue depth indicates shallow workload, it increases transmission frequency to maintain reaction efficiency; when queue depth is deep, it reduces frequency to improve processing efficiency, creating a dynamic balance

Inventive Principle:
Principle #15Dynamics

3Extent of automation

If the host system frequently switches between command processing and checking procedures, then it can handle more commands, but the system loading increases and data processing performance decreases

Engineering Contradiction:
Improvecommand handling capabilityVSAvoiddata processing performance
Core Design Contradiction:
Extent of automationVSProductivity

Solution Approach 1:

The patent applies partial action by selectively transmitting interruption messages based on command queue depth. Instead of transmitting after every single command completion (which would cause excessive switching), it transmits after a subset of commands or based on timeout conditions, reducing the frequency of procedure switches while still maintaining adequate system responsiveness

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10866887B2Memory management method, memory storage device and memory control circuit unit
Publication Date: 2020.12.15 PHISON ELECTRONICS
  • US10866887B2 patent drawing
  • US10866887B2 patent drawing
  • US10866887B2 patent drawing

AI summary

A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first command and performing a first operation corresponding to the first command; transmitting a completion message to a host system corresponding to a completion of the first operation; detecting command processing information; determining a transmission mode of an interruption message according to the command processing information; and transmitting the interruption message to the host system according to the transmission mode.