Memory Control Device Latency-Based Command Issuance
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Solution Overview
Problem
The increasing number of banks in DDR memory systems leads to performance degradation due to access conflicts and increased circuit complexity in memory control devices, which are exacerbated by the need to check busy states across multiple request queue entries and busy states, resulting in a larger circuit scale.
Innovation Solution
The implementation of a memory control device that processes access requests by using pending entries with latency information, where a value indicating latency is set and subtracted for each unit of time, allowing for controlled command issuance based on latency information, thereby reducing the circuit scale and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of banks in DDR memory is increased to improve memory throughput, then memory throughput is improved, but circuit complexity and access conflicts increase leading to performance degradation
Solution Approach 1:
The patent pre-calculates and stores latency information for each pending entry in the request queue before commands are issued. By preparing latency values in advance for each entry, the system avoids complex real-time calculations when commands need to be issued, thus maintaining performance with increased banks while controlling circuit complexity.
Solution Approach 2:
The patent uses a simplified latency information structure that can be copied and stored in each pending entry without requiring complex comparator circuits. Each entry maintains its own latency value, allowing parallel processing without extensive inter-entry comparison logic, thereby reducing overall circuit complexity while supporting multiple banks.
2Reliability
If extensive comparator circuits are used to check busy states across multiple request queue entries, then access conflict detection is improved, but circuit scale increases
Solution Approach 1:
The patent extracts the latency checking function from a complex global comparator system and embeds it individually in each pending entry. Each entry independently maintains and checks its own latency information, eliminating the need for extensive cross-entry comparator circuits while maintaining reliable access conflict detection.
Solution Approach 2:
Each pending entry autonomously manages its own latency information without requiring external comparator intervention. The entry independently tracks its latency value and determines when its command can be issued, reducing the overall circuit scale by eliminating centralized comparison logic while maintaining detection reliability.
3Productivity
If bank switching is implemented to observe penalties in continuous DDR memory access, then access penalties are reduced, but control complexity increases
Solution Approach 1:
The patent changes the control approach from complex bank switching logic to a parameter-based system where each pending entry stores latency information. The control unit simply compares latency parameters to determine command issuance timing, avoiding complex bank state tracking while maintaining access efficiency through parameter-driven control.
Data Source
AI summary
An information processing device include: a memory; and a processor coupled to the memory and configured to: receive an access request directed to an access target and sets the access request in any one of a plurality of pending entries each of which includes latency information; issue a command that corresponds to the access request; control issuance of the command on a basis of the latency information of the any one of the pending entries; set a value that indicates latency for the access request in the latency information of the any one of the pending entries; and subtract a predetermined value from the latency information of the any one of the pending entries for each unit of time.